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fn6715 rev 0.00 page 1 of 39 may 22, 2008 fn6715 rev 0.00 may 22, 2008 isl6322g two-phase buck pwm controller with integrated mosfet drivers, i 2c interface, and phase dropping datasheet the isl6322g two-phase pwm control ic provides a precision voltage regulat ion system for advanced microprocessors and memory. the integration of power mosfet drivers into the cont roller ic marks a departure from the separate pwm controller and driver configuration of previous multiphase product f amilies. by reducing the number of external parts, this i ntegration is optimized for a cost and space saving power management solution. one outstanding feature of this controller ic is its multi-processor compatibility, a llowing it to work with both in tel and amd microprocessors. inc luded are programmable vid codes for intel vr10, vr11, as well as amd dac tables. a unity gain, differentia l amplifier is provi ded for remote volta ge sensing, compensating for any p otential difference between remote and local grounds. the output voltage can also be positively or negatively offse t through the use of a single external resistor. the isl6322g includes an i 2 c interface, allowing the controller to communicate wit h other devices over an i 2 c bus. signals sent over this bus can command the isl6322g to adjust the number of active phases, voltage margining offset, phase switching frequenc y, overvoltage protection levels, and can select the i ntegrated driver adaptive dead time scheme. the isl6322g also includes advanced control loop features for optimal transient respon se to load apply and removal. one of these features is highly accurate, fully differential, continuous dcr current sens ing for channel-current balance. active pulse positi oning (app) modulation is another unique feature, allowing for quicker init ial response to high di/dt load transients. this controller also allows the user the flexibility to choose between phase detect or lgate detect adaptiv e dead time schemes. this ability allows t he isl6322g to be used in a multitude of applications where either scheme is required. protection features of this c ontroller ic include a set of sophisticated overvoltage, u ndervoltage, and overcurrent protection. furthermore, the isl6322g includes protection against an open circuit on th e remote sensing inputs. combined, these features provid e advanced prote ction for the microprocessor and power system. features ? integrated multiphas e power conversion - 2-phase or 1-phase operat ion with internal drivers ? phase dropping for higher efficiency at low output current loads ? precision core voltage regulation - differential remote voltage sensing - 0.5% system accuracy over-temperature - adjustable reference-voltage offset ? optimal transient response - active pulse position ing (app) modulation - adaptive phase alignment (apa) ? fully differential, continuous dcr current sensing - precision channel-current balancing ?i 2 c interface - phase dropping - voltage margining offset - switching frequency adjustment - overvoltage protecti on level adjustment - selects adaptive dead time scheme ? user selectable i 2 c slave only device address: 1000_110x or 1000_111x ? user selectable adaptive dead time scheme - phase detect or lgate detect for application flexibility ? variable gate drive bias: 5v to 12v ? multi-processor compatible - intel vr10 and vr11 modes of operation - amd mode of operation ? microprocessor voltag e identification inputs -8-bit dac - selectable between intels extended vr10, vr11, amd 5-bit, and amd 6-bit dac tables - dynamic vid technology ? maximum allowable output voltage of 1.6v ? overcurrent protection ? multi-tiered overvoltage protection ? digital soft-start ? selectable operation frequ ency up to 1.5mh z per phase ? pb-free (rohs compliant)
isl6322g fn6715 rev 0.00 page 2 of 39 may 22, 2008 pinout isl6322g (48 ld qfn) top view ordering information part number (note) part marking temp. (c) package (pb-free) pkg. d wg. # isl6322gcrz* isl6322g crz 0 to +70 48 ld 7x7 qfn l48.7x7 ISL6322GIRZ* isl6322g irz -40 to +85 48 ld 7x7 qfn l48.7x7 *add -t suffix for tape and reel. please refer to tb347 for d etails on reel specifications. note: these intersil pb-free plastic packaged products employ sp ecial pb-free material sets, molding compounds/die attach mater ials, and 100% matte tin plate plus anneal (e3 termination finish, which is ro hs compliant and compatible with both snpb and pb-free solderin g operations). intersil pb-free products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-free requirements of ipc/je dec j std-020. vid4 vid6 vid7 fs nc nc vid5 nc nc nc nc vid3 vid2 vid1 vid0 vrsel scl sda ss/rst/a0 vcc 1 48 2 3 4 5 6 7 8 9 10 36 35 34 33 32 31 30 29 28 27 47 46 45 44 43 42 41 40 39 13 14 15 16 17 18 19 20 21 22 en isen1+ isen1- phase1 ugate1 boot1 lgate1 pvcc lgate2 boot2 comp fb iout vdiff rgnd vsen isen2+ isen2- nc nc 49 gnd 23 24 en_ph2 nc ref ofs 11 12 nc pgood 38 37 26 25 ugate2 phase2
isl6322g fn6715 rev 0.00 page 3 of 39 may 22, 2008 block diagram undervoltage driver vrsel dynamic vid d/a vid7 vid6 vid5 vid4 vid3 vid2 e/a ref fb offset ofs comp rgnd vsen vdiff ? 1 n ? pwm1 ? boot1 ugate1 phase1 lgate1 pvcc boot2 ugate2 phase2 lgate2 clock and generator modulator soft-start and fault logic ph2 detect vcc reset power-on 0.85v en fs pgood gnd 0.2v x1 vid1 vid0 en_ph2 ch1 current sense channel current balance overvoltage detection logic pwm2 mode/dac select isen1- isen1+ isen2- isen2+ ch2 current sense i avg mosfet driver mosfet load apply transient enhancement i trip waveform i 2 c logic ss/rst/a0 sda scl open sense line prevention and current limit iout ocp ocp 2.0v and i 2 c ocp ocp i sen1 i sen2 i sen1 +i sen2
isl6322g fn6715 rev 0.00 page 4 of 39 may 22, 2008 isl6322g integrated dr iver block diagram simplified i 2 c bus architecture through shoot- protection boot ugate phase lgate logic control gate pvcc 10k ? pwm soft-start and fault logic drsel 20k ? +5v r ss r ss isl6322g scl sda a0 slave address: ic #2 slave scl sda ic #1 slave scl sda scl master i 2 c bus sda +5v +5v 1000_110x isl6322g scl sda a0 slave address: 1000_111x note: pin a0 selects the slave address for the isl6322g
isl6322g fn6715 rev 0.00 page 5 of 39 may 22, 2008 typical application - isl6322g vid4 vid5 pgood vid3 vid2 vid1 vcc isl6322g vid0 fs ofs ref load vrsel en +12v gnd vid6 vid7 +5v isen2- isen2+ isen1- isen1+ fb comp vsen rgnd vdiff +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc ss/rst/a0 scl sda en_ph2 iout nc
isl6322g fn6715 rev 0.00 page 6 of 39 may 22, 2008 absolute maximum ratings supply voltage, vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6v supply voltage, pvcc . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +15v boot voltage, v boot . . . . . . . . . . . . . . gnd - 0.3v to gnd + 36v boot to phase voltage, v boot - phase . . . . . -0.3v to 15v (dc) -0.3v to 16v (<10ns, 10j) phase voltage, v phase . . . . . . . gnd - 0.3v to 15v (pvcc = 12) gnd - 8v (<400ns, 20j) to 24v (<200ns, v boot - phase = 12v) ugate voltage, v ugate . . . . . . . . v phase - 0.3v to v boot + 0.3v v phase - 3.5v (<100ns pulse width, 2j) to v boot + 0.3v lgate voltage, v lgate . . . . . . . . . . . gnd - 0.3v to pvcc + 0.3v gnd - 5v (<100ns pulse width, 2j) to pvcc + 0.3v input, output, or i/o voltage . . . . . . . . . gnd - 0.3v to v cc + 0.3v thermal information thermal resistance ? ja (c/w) ? jc (c/w) qfn package (notes 1, 2) . . . . . . . . . . 27 2.5 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +1 50c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp recommended operating conditions vcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+5v 5% pvcc supply voltage . . . . . . . . . . . . . . . . . . . . . . . +5v to 12v 5% ambient temperature isl6322gcrz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c ISL6322GIRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c caution: do not operate at or near the maximum ratings listed fo r extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured in free air with the component mounted on a high e ffective thermal conductivity t est board with direct attach f eatures. see tech brief tb379. 2. for ? jc , the case temp location is the center of the exposed metal p ad on the package underside. 3. limits established by characte rization and are not production tested. electrical specifications recommended operating conditions, parameters with min and/or ma x limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by c haracterization and are not production tested. parameter test conditions min typ max units bias supplies input bias supply current i vcc ; en = high 15 20 25 ma gate drive bias current - pvcc pin i pvcc ; en = high 2 4.3 6 ma vcc por (power-on reset) thres hold vcc rising 4.25 4.38 4.50 v vcc falling 3.75 3.88 4.00 v pvcc por (power-on reset) threshold pvcc rising 4.25 4.38 4.50 v pvcc falling 3.60 3.88 4.00 v pwm modulator oscillator fr equency accuracy, f sw r t = 100k ? ( 0.1%) 225 250 275 khz adjustment range of switching frequency (note 3) 0.08 1.0 mhz oscillator ramp amplitude, v p-p (note 3) 1.50 v control thresholds en rising threshold 0.85 v en hysteresis 110 mv en_ph2 input high voltage 3.0 v en_ph2 input low voltage 2.0 v comp shutdown threshold comp falling 0.1 0.2 0.3 v reference and dac system accuracy (1.000v to 1.600v) -0.5 0.5 % system accuracy (0.600v to 1.000v) -1.0 1.0 % system accuracy (0.375v to 0.600v) -2.0 2.0 % dac input low voltage (vr10, vr11) 0.4 v
isl6322g fn6715 rev 0.00 page 7 of 39 may 22, 2008 dac input high voltage (vr10, vr11) 0.8 v dac input low voltage (amd) 0.6 v dac input high voltage (amd) 1.0 v pin-adjustable offset ofs sink current accuracy (negative offset) r ofs = 10k ?? from ofs to gnd 37.0 40.0 43.0 a ofs source current accura cy (positive offset) r ofs = 30k ?? from ofs to vcc 50.5 53.5 56.5 a error amplifier dc gain r l = 10k to ground, (note 3) 96 db gain-bandwidth product c l = 100pf, r l = 10k to ground, (note 3) 20 mhz slew rate c l = 100pf, load = 400a, (note 3) 8 v/s maximum output voltage load = 1ma 3.90 4.20 v minimum output voltage load = -1ma 1.30 1.5 v soft-start ramp soft-start ramp rate vr10/vr11, r s = 100k ?? 1.563 mv/s amd 2.063 mv/s adjustment range of soft-start ramp rate (note 3) 0.625 6.25 mv/s pwm output pwm output voltage low threshold i load = 500a 0.5 v pwm output voltage high threshold i load = 500a 4.5 v current sensing current sense resistance, r isen t = +25c 297 300 303 ? sensed current tolerance isen1 + isen2 = 80a 69 78 85 a overcurrent protection overcurrent trip level - average channel 1-phase normal operatio n 110 126 140 a 2-phase normal operation 224 252 280 a 1-phase dynamic vid change 142 164 184 a 2-phase dynamic vid change 290 327 360 a overcurrent trip level - indivi dual channel normal operation 150 1 77 204 a dynamic vid change (note 3) 209.4 238 266.6 a protection undervoltage threshold vsen falling 55 60 65 %vid undervoltage hysteresis vsen rising 10 %vid overvoltage threshold during soft-start vr10/vr11 1.24 1.28 1.32 v amd 2.13 2.20 2.27 v overvoltage threshold (default) vsen rising vdac + 225mv vdac + 250mv vdac + 275mv v overvoltage threshold (alternate) vsen rising vdac + 150mv vdac + 175mv vdac + 200mv v overvoltage hysteresis vsen falling 100 mv electrical specifications recommended operating conditions, parameters with min and/or ma x limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by c haracterization and are not production tested. (continued) parameter test conditions min typ max units
isl6322g fn6715 rev 0.00 page 8 of 39 may 22, 2008 timing diagram switching time (note 3) ugate rise time t rugate; v pvcc = 12v, 3nf load, 10% to 90% 26 ns lgate rise time t rlgate; v pvcc = 12v, 3nf load, 10% to 90% 18 ns ugate fall time t fugate; v pvcc = 12v, 3nf load, 90% to 10% 18 ns lgate fall time t flgate; v pvcc = 12v, 3nf load, 90% to 10% 12 ns ugate turn-on non-overlap t pdhugate ; v pvcc = 12v, 3nf load, adaptive 10 ns lgate turn-on non-overlap t pdhlgate ; v pvcc = 12v, 3nf load, adaptive 10 ns gate drive resistance (note 3) upper drive source resistance v pvcc = 12v, 15ma source current 2.0 ? upper drive sink resistance v pvcc = 12v, 15ma sink current 1.65 ? lower drive source resistance v pvcc = 12v, 15ma source current 1.25 ? lower drive sink resistance v pvcc = 12v, 15ma sink current 0.80 ? over temperature shutdown (note 3) thermal shutdown setpoint 160 c thermal recovery setpoint 100 c electrical specifications recommended operating conditions, parameters with min and/or ma x limits are 100% tested at +25c, unless otherwise specified. tem perature limits established by c haracterization and are not production tested. (continued) parameter test conditions min typ max units ugate lgate t flgate t pdhugate t rugate t fugate t pdhlgate t rlgate
isl6322g fn6715 rev 0.00 page 9 of 39 may 22, 2008 functional pin description vcc vcc is the bias suppl y for the ics small-signal circuitry. connect this pin to a +5v su pply and decouple using a quality 0.1 f ceramic capacitor. pvcc this pin is the power supply pin for channel 1 and 2s mosfet drive, and can be connected to any voltage from +5v to +12v depending on the desired mosfet gate-drive level. decouple this pin with a quality 1. 0f ceramic capacitor. gnd gnd is the bias and refer ence ground for the ic. en this pin is a threshold-sensitive (approximately 0.85v) enable input for the controller. held l ow, this pin disables controlle r operation. pulled high, the pin enables the controller for operation. fs a resistor, placed from fs t o ground, sets the switching frequency of the controller. vid0, vid1, vid2, vid3, vi d4, vid5, vid6, and vid7 these are the inputs for the internal dac that provides the reference voltage for output regulation. these pins respond to ttl logic thresholds. these pin s are internally pulled high, to approximately 1.2v, by 40a int ernal current sour ces for intel modes of operation, and pulled lo w by 20a internal current sources for amd modes of ope ration. the internal pull-up current decreases to 0 as th e vid voltage approaches the internal pull-up voltage. all vid pins are compatible with external pull-up voltages not exceeding the ics bias voltage (vcc). vrsel the state of t his pin selects which of the available dac tables will be used to decode the vid inputs and puts the controller into the corresponding mode of operation. for vr10 mode of operation vrsel should be less then 0.6v. the vr11 mode of operation can be selected by setting vrsel between 0.6v and 3.0v, and amd compliance is sel ected if this pi n is between 3.0v and vcc. vsen and rgnd vsen and rgnd are inputs to the precision differential remote-sense amplifier and should be connected to the sense pins of the remote load. vdiff vdiff is the output of the differ ential remote-sense amplifier. the voltage on this pin is equal to the difference between vsen and rgnd. fb and comp these pins are the internal error amplifier inverting input and output respectively. fb, vdiff , and comp are tied together through external r-c networks to compensate the regulator. iout the iout pin is the total c hannel-sense current output. connecting this pin through a resistor to ground allows the controller to set the overcurrent protection trip level. this p in pin can also be used as a load current indicator to monitor what the output lo ad current is. since the current coming out of the iout pin is equal to the addition of channel 1 and 2s sense currents, the current will be twice as large in 2-phase mode then when in single phase mode. ref the ref input pin is the positiv e input of the error amplifier. it is internally connected to the dac output through a 1k ? resistor. a capacitor is used between the ref pin and ground to smooth the voltage trans ition during dynamic vid operations. ofs the ofs pin provides a means to program a dc current for generating an offset voltage ac ross the resistor between fb and vdiff. the offset current i s generated via an external resistor and precision internal voltage references. the polarit y of the offset is selected by connecting the resistor to gnd or vcc. for no offset, the ofs pin should be left unconnected. isen1-, isen1+, i sen2-, and isen2+ these pins are used for di fferentially sensing the corresponding channel output currents. the sensed currents are used for channel-current balancing and protection. connect isen1- and isen2-to the node between the rc sense elements surrounding the inductor of their respective channel. tie the isen+ pins to the vcore side of their corresponding channels sense capacitor. ugate1 and ugate2 connect these pins to the c orresponding upper mosfet gates. these pins are used t o control the upper mosfets and are monitored for shoot -through prevent ion purposes. boot1 and boot2 these pins provide the bias voltage for the corresponding upper mosfet drives. connect these pins to appropriately-chosen external bootstrap capacitors. internal bootstrap diodes conn ected to the pvcc pins provide the necessary bootstrap charge. phase1 and phase2 connect these pins to the sou rces of the corresponding upper mosfets. these pins a re the return path for the upper mosfet drives.
isl6322g fn6715 rev 0.00 page 10 of 39 may 22, 2008 lgate1 and lgate2 these pins are used to control the lower mosfets. connect these pins to the correspon ding lower mosfets gates. en_ph2 this pin is a digital logic in put which tells the controller to operate in single phase or 2-phase mode. the number of active phases can be changed while the controller is operating by changing the state of this pin. tying this pin high commands the part to operate in single phase mode only. if en_ph2 is tied low t he part can operate in either single phase or 2-phase mode depending on th e state of bit 6 of i 2 c register 2. the default i 2 c setting is 2-phase mode, so if bit 6 of register 2 is not changed tieing en_ph2 low commands the controller t o operate in 2-phase mode. if en_ph2 is tied high the contro ller will ignore the state of bit 6 in register 2 and will not allow the i 2 c interface to control the number of channels firing. ss/rst/a0 this pin has three different f unctions associat ed with it. the first is that a resistor (r ss ), placed from this pin to ground, or vcc, will set the soft-start r amp slope for the intel dac modes of operation. refer to e quations 15 and 16 for proper resistor calculation. the second function of this pin i s that it selects which of the two 8-bit slave i 2 c addresses the c ontroller will use. connecting the r ss resistor on this pin to ground will choose slave address one( 1000_110x), while connecting this resistor to vcc will select slave address two(1000_111x). the third functi on of this pin is a reset to the i 2 c registers. during normal operation of the part, if this pin is ever grounded, all of the i 2 c registers are reset to 0000_0000. an open drain device is reco mmended as the means of grounding this pin for resetting the i 2 c registers. scl connect this pin to the clock signal for the i 2 c bus, which is a logic level input signal. the clock signal tells the controll er when data is available on the i 2 c bus. sda connect this pin to the bidi rectional data line of the i 2 c bus, which is a logic level input/output signal. all i 2 c data is sent over this line, including the a ddress of the device the bus is trying to communicate with, a nd what functions the device should perform. pgood during normal operation pgood indicates whether the output voltage is within specified overvoltage and undervoltage limits. if the output v oltage exceeds these limits or a reset event o ccurs (such as an overcurrent event), pgood is pulled low. pgood is always low prior to the end of soft-start. nc these are no connect pins. they should be left floating. operation multiphase power conversion microprocessor load current p rofiles have changed to the point that using single-phase regulators is no longer a viable solution. designing a regulato r that is cost-effective, thermally sound, and efficient has become a challenge that only multiphase converters can accomplish. the isl6322g controller helps sim plify implementation by integrating vital functions and requi ring minimal external components. the block diagram on page 3 provides a top level view of multiphase power conversion us ing the isl6322g controller. interleaving the switching of each channel in a multiphase converter is timed to be symmetrically out o f phase with each of the other channels. for example, in a 3-phase converter, each channel switche s 1/3 cycle after the previous channel and 1/3 cycle before the following channel. as a result, the 3-phase converter has a com bined ripple frequency 3x greater than the ripple frequency of any one phase. in addition, the peak-to-peak amplitude of the combined inductor currents is reduced in proportion to the number of phases (equations 1 and 2). increased ripple frequency and lower ripple amplitude mean th at the designer can use less per-channel inductance and lo wer total output capacitance for any performance specification. figure 1 illustrates the multip licative effect o n output ripple frequency. the three channel currents (i l1 , i l2 , and i l3 ) combine to form the ac rip ple current and the dc load current. the ripple component has 3x the ripple frequency of each individual channel-current. each pwm pulse is figure 1. pwm and inductor-current waveforms for 3-phase converter 1 s/div pwm2, 5v/div pwm1, 5v/div i l2 , 7a/div i l1 , 7a/div i l1 + i l2 + i l3 , 7a/div i l3 , 7a/div pwm3, 5v/div
isl6322g fn6715 rev 0.00 page 11 of 39 may 22, 2008 terminated 1/3 of a cycle after the pwm pulse of the previous phase. the peak-to-peak current for each phase is about 7a, and the dc components of the inductor currents combine to feed the load. to understand the reduction of ripple current amplitude in the multiphase circuit, examine the equation representing an individual channel peak-to-peak inductor current. in equation 1, v in and v out are the input and output voltages respectively, l is the single-channel inductor value, and f s is the switching frequency. the output capacitor s conduct the ripp le component of the inductor current. in the case o f multiphase converters, the capacitor current is the sum o f the ripple currents from each of the individual channels. compare equation 1 to the expression for the peak-to-peak current after the summation of n symmetrically phase-shifted inductor currents in equation 2. peak-to-peak ri pple current decreases by an amount proportional to the number of channels. output voltage ripple is a function of capacitance, capacitor equivalent series resistanc e (esr), and inductor ripple current. reducing the inductor ripple current allows the designer to use fewer or less costly output capacitors. another benefit of interleavin g is to reduce input ripple current. input capacitance is determined in part by the maximum input ripple current. multiphase topologies can improve overall system cost and size by lowering input ripple current and allowing the designer to reduce the cost of input capacitance. the example in f igure 2 illustrates input currents from a three-phase c onverter combining to reduce the total input ripple current. the converter depicted in figure 2 delivers 1.5v to a 36a load from a 12v input. the rms inpu t capacitor current is 5.9a. compare this to a single-phase converter also stepping down 12v to 1.5v at 36a. the sin gle-phase conv erter has 11.9a rms input capacitor current. t he single-phase converter must use an input capacitor bank with twice the rms current capacity as the equivalent 3-phase converter. active pulse po sitioning (app) modulated pwm operation the isl6322g uses a proprieta ry active pulse positioning (app) modulation scheme to c ontrol the in ternal pwm signals that command each c hannels driver to turn their upper and lower mosfets on an d off. the time interval in which a pwm signal can occur is generated by an internal clock, whose cycle time is th e inverse of t he switching frequency set by the resistor between the fs pin and ground. the advantage of intersils proprietary active pulse positioning (app) mod ulator is that the pwm signal has the ability to turn on at any point d uring this pwm time interval, and turn off immediately after the pwm signal has transitioned high. this is im portant because is allows the controller to quickly respon d to output voltage drops associated with current load spi kes, while avoid ing the ring back affects associated wit h other modulation schemes. the pwm output state is driven by the position of the error amplifier output signal, v comp , minus the current correction signal relative to the proprie tary modulator ramp waveform as illustrated in figure 3. at the beginning of each pwm time interval, this modified v comp signal is compared to the internal modulator waveform. as long as the modified v comp voltage is lower then the modulator waveform voltage, the pwm signal is com manded low. the internal mosfet driver detects the low state of the pwm signal and turns off the upper mosfe t and turns on the lower synchronous mosfet. when the modified v comp voltage crosses the modulator ramp, t he pwm output transitions high, turning off the synchronous mosfet and turning on the upper mosfet. the pwm si gnal will remain high until the modified v comp voltage crosses th e modulator ramp again. when this occurs the pwm signal will t ransition low again. during each pwm time interva l the pwm signal can only transition high once. once pwm transitions high it can not transition high again until th e beginning of the next pwm time interval. this prevents the occurrence of double pwm pulses occurring during a single period. to further improve the transient response, isl6322g also implements intersils proprieta ry adaptive phase alignment (apa) technique, which turns on all phases together under transient events with large step current. with both app and apa control, isl6322g can achieve excellent transient performance and reduce t he demand on the output capacitors. i p-p v in v out C ?? v out ? lf s v ? in ? --------------------------------------------------------- - = (eq. 1) i cp-p ?? v in nv out ? C ?? v out ? lf s v ? in ? --------------------------------------------------------------- ---- - = (eq. 2) figure 2. channel input currents and input-capacitor rms current for 3-phase converter input-capacitor current, 10a/div 1s/div channel 3 input current 10a/div channel 1 input current 10a/div channel 2 input current 10a/div
isl6322g fn6715 rev 0.00 page 12 of 39 may 22, 2008 phase dropping the isl6322g has the ability t o change the number of active phases firing on-the-fly. this can be done through one of two ways; through the us e of the en_ph2 pi n, and through the i 2 c interface. the en_ph2 pin is a digital logi c input pin. tieing this pin high commands the part to operate in single phase mode only. if en_ph2 is tied low t he part can operate in either single phase or 2-phase mode depending on th e state of bit 6 of i 2 c register 2. when the co ntroller first powers up bit 6 is preset to 0, which commands the controller to operate in 2-phase mode. changing bit 6 to a 1 commands the controller to operate in single phase mode. for details on how to change the state of the i 2 c registers please refer to the i 2 c bus interface on page 26 . if en_ph2 is tied high, the controller will operate in s ingle phase mode only and will ignore the state of bit 6 in register 2, not allowing the i 2 c interface to contr ol the number of channels firing. once the isl6322g receives a signal to change the number of active phases it immediat ely responds by dropping or adding phase 2 with no delay. when dropping from 2-phase to single phase mode bot h lgate2 and ugate2 are immediately tied low. these signals will stay in this state unt il the controller is commanded to run in 2-phase mode again. at this point lgate2 and ugat e2 will be released to fire normally. channel-current balance one important benefit of multiphase operation is the thermal advantage gained by distributi ng the dissipated heat over multiple devices and greater ar ea. by doing this the designer avoids the complexity of drivi ng parallel mosfets and the expense of using expe nsive heat sinks an d exotic magnetic materials. in order to realize the thermal advantage, it is i mportant that each channel in a multiphase c onverter be controlled to carry equal amounts of current at any load level. to achieve this, the currents through e ach channel must be sampled every switching cycle. t he sampled currents, i n , from each active channel are summed together and divided by the number of active channels. t he resulting cycle average current, i avg , provides a measure of the total load-current demand on the converter durin g each switching cycle. channel-current balance is achieved by comparing the sampled current of each ch annel to the cycle average current, and making the proper adjustment to each channel pulse width based on the error. intersils patented current-balance method is illustrated in f igure 3, with error correction for channel 1 repres ented. in the figure, the cycle average current, i avg , is compared with the channel 1 sample, i 1 , to create an error signal i er . the filtered error signal modifies the pulse width commanded by v comp to correct any unba lance and force i er toward zero. the same method for error signal correction is applied to each active channel . continuous current sampling in order to realize proper cu rrent-balance, the currents in each channel are s ensed continuously every switching cycle. during this time the current-sense a mplifier uses the isen inputs to reproduce a signal proportional to the inductor current, i l . this sensed current, i sen , is simply a scaled version of the inductor current. the isl6322g supports inductor dcr current sensing to continuously sense each channels current for channel-current balance (see figure 4). the internal circuitry, shown in figure 5 represents channel n of an n-channel converter. this ci rcuitry is repeated for each channel in the converter, but may not be active depending on how many channels are operating. figure 3. channel-1 pwm function and current-balance adjustment ?? n i avg i sen2 ? - + + - + - f(s) pwm1 i sen1 v comp i er filter to gate control logic modulator ramp waveform figure 4. continuous current sampling time pwm i l i sen switching period
isl6322g fn6715 rev 0.00 page 13 of 39 may 22, 2008 . inductor windings have a characteristic distributed resistance or dcr (direct current resistance). for simplicity, the inductor dcr is considered as a separate lumped quantity, as shown in figure 5. the channel-current i l , flowing through the inductor , passes through the dcr. equation 3 shows the s-domain equivalent voltage, v l , across the inductor. a simple r-c network a cross the inductor (r 1 and c) extracts the dcr voltage, as shown in figure 5. the voltage across the sens e capacitor, v c , can be shown to be proportional to the channel-current i l , shown in equation 4. in some cases it may be necessary to use a resistor divider r-c network to sense the curren t through the inductor. this can be accomplished by pla cing a second resistor, r 2 , across the sense ca pacitor. in these cases the voltage across the sense capacitor, v c , becomes proportional to the channel-current i l , and the resistor divider ratio, k. if the r-c network components are selected su ch that the rc time constant matches t he inductor l/dcr time constant, then v c is equal to the voltage drop across the dcr multiplied by the ratio o f the resistor divider, k. if a resistor divider is not being used, the value for k is 1 . the capacito r voltage v c , is then replic ated across the sense resistor r isen . the current through r isen is proportional to the inductor cu rrent. equation 7 shows that the proportion betwe en the channel-curre nt and the sensed current (i sen ) is driven by the value of the sense resistor, the resistor divider ratio, and the dcr of the inductor. output voltage setting the isl6322g uses a digital t o analog converter (dac) to generate a reference voltage bas ed on the logic signals at the vid pins. the dac decodes the logic signals into one of the discrete voltages shown in t ables 2, 3, 4 and 5. in intel modes of operation, each vid pi n is pulled up to an internal 1.2v voltage by a weak cu rrent source (40a), which decreases to 0a as the voltage a t the vid pin varies from 0 to the internal 1.2v pull-up voltage. in amd modes of operation the vid pins are pulled low by a weak 20a current source. external pull-up resistors or active-high output stages can augment the pull-up current sources, up to a voltage of 5v. the isl6322g accommodates f our different dac ranges: intel vr10 (extended), intel vr11, amd k8/k9 5-bit, and amd 6-bit. the state of the vrsel and vid7 pins decide which dac version is active. refer to table 1 for a description of how to sele ct the desired dac version. figure 5. inductor dcr current sensing configuration i sen(n) - + isen-(n) sample isl6322g internal circuit v in ugate(n) r isen dcr l inductor r 1 v out c out - + v c (s) c i l - + v l (s) i sen(n) r 2* v c (s) + - *r 2 is optional isen+(n) lgate(n) mosfet driver v l s ?? i l sl dcr + ? ?? ? = (eq. 3) v c s ?? sl ? dcr ------------- 1 + ?? ?? sr 1 c ?? 1 + ?? ------------------------------------- - dcr i l ? ? = (eq. 4) table 1. isl6322g dac select table dac version vrsel pin vid7 pin vr10(extended) vrsel < 0.6v - vr11 0.8v < vrsel < 3.0v - amd 5-bit 3.0v < vrsel < vcc low amd 6-bit 3.0v < vrsel < vcc high table 2. vr10 (extended) voltage identification codes vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac 01010111. 60000 01010101. 59375 v c s ?? sl ? dcr ------------- 1 + ?? ?? s r 1 r 2 ? ?? r 1 r 2 + ----------------------- - c ?? 1 + ?? ?? ?? ------------------------------------------------------- - kdcri l ?? ? = (eq. 5) k r 2 r 2 r 1 + -------------------- - = (eq. 6) i sen ki l dcr r isen ----------------- - ?? = (eq. 7)
isl6322g fn6715 rev 0.00 page 14 of 39 may 22, 2008 01011011.58750 01011001.58125 01011111.57500 01011101.56875 01100011.56250 01100001.55625 01100111.55000 01100101.54375 01101011.53750 01101001.53125 01101111.52500 01101101.51875 01110011.51250 01110001.50625 01110111.50000 01110101.49375 01111011.48750 01111001.48125 01111111.47500 01111101.46875 10000011.46250 10000001.45625 10000111.45000 10000101.44375 10001011.43750 10001001.43125 10001111.42500 10001101.41875 10010011.41250 10010001.40625 10010111.40000 10010101.39375 10011011.38750 10011001.38125 10011111.37500 10011101.36875 10100011.36250 10100001.35625 10100111.35000 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac 10100101. 34375 10101011. 33750 10101001. 33125 10101111. 32500 10101101. 31875 10110011. 31250 10110001. 30625 10110111. 30000 10110101. 29375 10111011. 28750 10111001. 28125 10111111. 27500 10111101. 26875 11000011. 26250 11000001. 25625 11000111. 25000 11000101. 24375 11001011. 23750 11001001. 23125 11001111. 22500 11001101. 21875 11010011. 21250 11010001. 20625 11010111. 20000 11010101. 19375 11011011. 18750 11011001. 18125 11011111. 17500 11011101. 16875 11100011. 16250 11100001. 15625 11100111. 15000 11100101. 14375 11101011. 13750 11101001. 13125 11101111. 12500 11101101. 11875 11110011. 11250 11110001. 10625 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac
isl6322g fn6715 rev 0.00 page 15 of 39 may 22, 2008 11110111.10000 11110101.09375 1111101off 1111100off 1111111off 1111110off 00000011.08750 00000001.08125 00000111.07500 00000101.06875 00001011.06250 00001001.05625 00001111.05000 00001101.04375 00010011.03750 00010001.03125 00010111.02500 00010101.01875 00011011.01250 00011001.00625 00011111.00000 00011100.99375 00100010.98750 00100000.98125 00100110.97500 00100100.96875 00101010.96250 00101000.95625 00101110.95000 00101100.94375 00110010.93750 00110000.93125 00110110.92500 00110100.91875 00111010.91250 00111000.90625 00111110.90000 00111100.89375 01000010.88750 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac 01000000. 88125 01000110. 87500 01000100. 86875 01001010. 86250 01001000. 85625 01001110. 85000 01001100. 84375 01010010. 83750 01010000. 83125 table 3. vr11 voltage identification codes vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 00000000off 00000001off 000000101.6 0000 000000111.5 9375 000001001.5 8750 000001011.5 8125 000001101.5 7500 000001111.5 6875 000010001.5 6250 000010011.5 5625 000010101.5 5000 000010111.5 4375 000011001.5 3750 000011011.5 3125 000011101.5 2500 000011111.5 1875 000100001.5 1250 000100011.5 0625 000100101.5 0000 000100111.4 9375 000101001.4 8750 000101011.4 8125 000101101.4 7500 000101111.4 6875 000110001.4 6250 000110011.4 5625 000110101.4 5000 table 2. vr10 (extended) voltage identification codes (continued) vid4 vid3 vid2 vid1 vid0 vid5 vid6 vdac
isl6322g fn6715 rev 0.00 page 16 of 39 may 22, 2008 000110111.44375 000111001.43750 000111011.43125 000111101.42500 000111111.41875 001000001.41250 001000011.40625 001000101.40000 001000111.39375 001001001.38750 001001011.38125 001001101.37500 001001111.36875 001010001.36250 001010011.35625 001010101.35000 001010111.34375 001011001.33750 001011011.33125 001011101.32500 001011111.31875 001100001.31250 001100011.30625 001100101.30000 001100111.29375 001101001.28750 001101011.28125 001101101.27500 001101111.26875 001110001.26250 001110011.25625 001110101.25000 001110111.24375 001111001.23750 001111011.23125 001111101.22500 001111111.21875 010000001.21250 010000011.20625 table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 010000101.2 0000 010000111.1 9375 010001001.1 8750 010001011.1 8125 010001101.1 7500 010001111.1 6875 010010001.1 6250 010010011.1 5625 010010101.1 5000 010010111.1 4375 010011001.1 3750 010011011.1 3125 010011101.1 2500 010011111.1 1875 010100001.1 1250 010100011.1 0625 010100101.1 0000 010100111.0 9375 010101001.0 8750 010101011.0 8125 010101101.0 7500 010101111.0 6875 010110001.0 6250 010110011.0 5625 010110101.0 5000 010110111.0 4375 010111001.0 3750 010111011.0 3125 010111101.0 2500 010111111.0 1875 011000001.0 1250 011000011.0 0625 011000101.0 0000 011000110.9 9375 011001000.9 8750 011001010.9 8125 011001100.9 7500 011001110.9 6875 011010000.9 6250 table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac
isl6322g fn6715 rev 0.00 page 17 of 39 may 22, 2008 011010010.95625 011010100.95000 011010110.94375 011011000.93750 011011010.93125 011011100.92500 011011110.91875 011100000.91250 011100010.90625 011100100.90000 011100110.89375 011101000.88750 011101010.88125 011101100.87500 011101110.86875 011110000.86250 011110010.85625 011110100.85000 011110110.84375 011111000.83750 011111010.83125 011111100.82500 011111110.81875 100000000.81250 100000010.80625 100000100.80000 100000110.79375 100001000.78750 100001010.78125 100001100.77500 100001110.76875 100010000.76250 100010010.75625 100010100.75000 100010110.74375 100011000.73750 100011010.73125 100011100.72500 100011110.71875 table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac 100100000.7 1250 100100010.7 0625 100100100.7 0000 100100110.6 9375 100101000.6 8750 100101010.6 8125 100101100.6 7500 100101110.6 6875 100110000.6 6250 100110010.6 5625 100110100.6 5000 100110110.6 4375 100111000.6 3750 100111010.6 3125 100111100.6 2500 100111110.6 1875 101000000.6 1250 101000010.6 0625 101000100.6 0000 101000110.5 9375 101001000.5 8750 101001010.5 8125 101001100.5 7500 101001110.5 6875 101010000.5 6250 101010010.5 5625 101010100.5 5000 101010110.5 4375 101011000.5 3750 101011010.5 3125 101011100.5 2500 101011110.5 1875 101100000.5 1250 101100010.5 0625 101100100.5 0000 11111110off 11111111off table 3. vr11 voltage identification codes (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 vdac
isl6322g fn6715 rev 0.00 page 18 of 39 may 22, 2008 table 4. amd 5-bit voltage identification codes vid4 vid3 vid2 vid1 vid0 vdac 11111off 111100.800 111010.825 111000.850 110110.875 110100.900 110010.925 110000.950 101110.975 101101.000 101011.025 101001.050 100111.075 100101.100 100011.125 100001.150 011111.175 011101.200 011011.225 011001.250 010111.275 010101.300 010011.325 010001.350 001111.375 001101.400 001011.425 001001.450 000111.475 000101.500 000011.525 000001.550 table 5. amd 6-bit voltage identification codes vid5 vid4 vid3 vid2 vid1 vid0 vdac 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 table 5. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac
isl6322g fn6715 rev 0.00 page 19 of 39 may 22, 2008 voltage regulation the integrating co mpensation network shown in figure 6 insures that the steady-state error in the output voltage is limited only to the e rror in the reference voltage (output of the dac) and offset errors in the ofs current source, remote-sense and error amplif iers. intersil specifies the guaranteed tolerance of the isl6322g to include the combined tolerances of each of these elements. the output of the error amplifier, v comp , is compared to the triangle waveform to generat e the pwm signals. the pwm signals control the timing of the i nternal mosfet drivers and regulate the converter output so that the voltage at fb is equal to the voltage at ref. t his will regulat e the output voltage to be equal to equation 8. the internal and external circuitry that controls voltage regulation is illustrated in figure 6. the isl6322g incorpor ates an internal dif ferential remote- sense amplifier in the feedback path. the amplifier removes the voltage error encountered when measuring the output voltage relative to t he controller ground reference point resulting in a more accura te means of sensing output voltage. connect the micropr ocessor sense pins to the non-inverting input, vsen, and inverting input, rgnd, of the remote-sense amplifier. t he remote-sense output, v diff , is connected to the inverting input of the error amplifier through an external resistor. output-voltage offset programming the isl6322g allows the desig ner to accurately adjust the offset voltage by connecting a resistor, r ofs , from the ofs pin to vcc or gnd. when r ofs is connected between ofs and vcc, the voltage across i t is regulated to 1.6v. this causes a proportional current (i ofs ) to flow into the fb pin. if r ofs is connected to ground, t he voltage across it is regulated to 0.4v, and i ofs flows out of the fb pin. the offset current flowing through the resistor between vdiff and fb will generate the desired offset voltage which is equal to the product (i ofs x r fb ). these functions are shown in figures 7 and 8. once the desired output offset voltage has been determined, use equations 9 and 10 to set r ofs : for negative offset (connect r ofs to gnd): for positive offset (connect r ofs to vcc): 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750 table 5. amd 6-bit voltage identification codes (continued) vid5 vid4 vid3 vid2 vid1 vid0 vdac v out v ref v ofs C = (eq. 8) figure 6. output voltage and load-line regulation with offset adjustment external circuit isl6322 internal circuit comp r c r fb fb vdiff vsen rgnd - + v ofs error - + v out + differential remote-sense amplifier v comp c c ref c ref - + v out - vid dac 1k amplifier i ofs (eq. 9) r ofs 0.4 r fb ? v offset -------------------------- = (eq. 10) r ofs 1.6 r fb ? v offset -------------------------- =
isl6322g fn6715 rev 0.00 page 20 of 39 may 22, 2008 dynamic vid modern microprocessors need to make changes to their core voltage as part of normal operation. they direct the isl6322g to do this by making changes to the vid inputs. the isl6322g is required to monitor the dac inputs and respond to on-the-fly vid changes in a controlled manner, supervising a safe output voltage transition without discontinuity or disruption. the dac mode the isl6322g is operating in determines how the controller responds to a dynamic vid change. intel dynamic vid transitions when in intel vr10 or vr11 m ode, the isl6322g checks the vid inputs on the positiv e edge of an in ternal 3mhz clock. if a new code is established and it remains stable for 3 consecutive readings (1s to 1.33s), the isl6322g recognizes the new code and changes the internal dac reference directly to the new level. the intel processor controls the vid transitio ns and is responsible for incrementing or decrementing one vid step at a time. in vr10 and vr11 settings, th e isl6322g will immediately change the internal dac reference to the new requested value as soon as the reques t is validated, which means the fastest recommended rate at which a bit change can occur is once every 2s. in cases wher e the reference step is too large, the sudden change ca n trigger overcurrent or overvoltage events. in order to ensure t he smooth transition of output voltage during a vr10 or v r11 vid change, a vid step change smoothing network is required. t his network is composed of an internal 1k ? resistor between the dac and the ref pin, and the external capacitor c ref , between the ref pin and ground. the selection of c ref is based on the time duration for 1-bit vid change and t he allowable delay time. assuming the microprocessor controls the vid change at 1-bit every t vid , the relationship between c ref and t vid is given by equation 11. as an example, for a vid step change rate of 5s per bit, the value of c ref is 5600pf based on equation 11. amd dynamic vid transitions when running in amd 5-bit or 6-bit modes of operation, the isl6322g responds differently t o a dynamic vid change than when in intel vr10 or vr11 mode. in the amd modes, the isl6322g still checks the vid in puts on the positive edge of an internal 3mhz clock. in t hese modes the vid code can be changed by more than a 1-bit step at a time. if a new code is established and it remains stabl e for 3 consecutive readings (1s to 1.33s), the isl6322g recognizes the change and begins slewing the dac in 6 .25mv steps at a stepping frequency of 330khz until th e vid and dac are equal. thus, the total time require d for a vid change, t dvid , is dependent only on the size of the vid change ( ? v vid ). the time required for a isl 6322g-based converter in amd 5-bit dac configuration to m ake a 1.1v to 1.5v reference voltage change is about 194 s, as calculated using equation 12. in order to ensure t he smooth transition of output voltage during an amd vid change, a v id step change smoothing network is required. this network is composed of an internal figure 7. positive offset output voltage programming e/a fb ofs vcc + 1.6v vcc r ofs r fb vdiff isl6322g ref v ofs + - i ofs i ofs 1:1 current mirror - figure 8. negative offset output voltage programming e/a fb ofs gnd + 0.4v r ofs r fb vdiff isl6322g ref v ofs + - i ofs i ofs 1:1 current mirror vcc - gnd c ref 0.001 s ?? t vid ? = (eq. 11) (eq. 12) t dvid 1 330 10 3 ? ------------------------- - v vid ? 0.00625 --------------------- ?? ?? ? =
isl6322g fn6715 rev 0.00 page 21 of 39 may 22, 2008 1k ? resistor between the dac and the ref pin, and the external capacitor c ref , between the ref pin and ground. for amd vid transitions c ref should be a 1000pf capacitor. user selectable adaptive deadtime control techniques the isl6322g integrated drivers incorporate two different adaptive deadtime control tech niques, which the user can choose between. both of these control techniques help to minimize deadtime, resulting in high efficiency from the reduce d freewheeling time of the lower mosfet body-diode conduction, and both help to prevent the upper and lower mosfets from conducting simultaneously. this is accomplished by ensuring eith er rising gate turns on its mosfet with minimum and sufficient delay after the other has turned off. the difference between the tw o adaptive deadtime control techniques is the method in wh ich they detect that the lower mosfet has transitioned off in order to turn on the upper mosfet. the state of the internal i 2 c registers determines which of the two control techniques is active (refer beginning on page 27 for details of controlling deadtime control with i 2 c). the default setting is phase detect. if the phase detect scheme is chosen, the voltage on the phase pin is monitored to det ermine if the lower mosfet has transitioned off or not. choosi ng the lgate detect scheme instructs the controll er to monitor the vo ltage on the lgate pin to determine if the lower mosfet has turned off or not. for both schemes, the method for determining whether the upper mosfet has transitioned of f in order to signal to turn on the lower mosfet is the same. phase detect for the phase detect scheme, during turn -off of the lower mosfet, the phase voltage is monitored until it reaches a -0.3v/+0.8v (for ward/reverse inductor cu rrent). at this time th e ugate is released to rise. an au to-zero comparator is used to correct the r ds(on) drop in the phase volt age preventing false detection of the -0.3v phase level during r ds(on) conduction period. in the case of zero curr ent, the ugate is released afte r 35ns delay of the lgate dro pping below 0.5v. when lgate first begins to transition low, this quick transition can distu rb the phase node and cause a false trip, so there is 20ns of blanking time once lgate fall s until phase is monitored. once the phase is high, the advanced adaptive shoot-through circuitry mo nitors the phase and ugate voltages during a pwm fallin g edge and the subsequent ugate turn-off. if either the u gate falls to less than 1.75v above the phase or the phase fall s to less than +0.8v, the lgate is released to turn-on. lgate detect for the lgate detect scheme, during turn-off of the lower mosfet, the lgate voltage is monitored until it reaches 1.75v. at this time the ugat e is released to rise. once the phase is high, the advanced adaptive shoot-through circuitry mo nitors the phase and ugate voltages during a pwm falli ng edge and the subsequent ugate turn-off. if either the ug ate falls to less than 1.75v above the phase or the phase fa lls to less than +0.8v, the lgate is release d to turn-on. internal bootstrap device all three integrated drivers feature an inte rnal bootstrap schottky diode. simply adding an external capacitor across the boot and phase pins compl etes the bootstrap circuit. the bootstrap function is als o designed to prevent the bootstrap capacitor from o vercharging due to the large negative swing at the phase n ode. this reduces voltage stress on the boot to phase pins. the bootstrap capacitor must have a maximum voltage rating above pvcc + 4v and its capacitance value can be chosen from equation 13: where q g1 is the amount of gate charge per upper mosfet at v gs1 gate-source voltage and n q1 is the number of control mosfets. the ? v boot_cap term is defined as the allowable droop in the ra il of the upper gate drive. gate drive voltage versatility the isl6322g provides the user flexibility in choosing the gate drive voltage for efficien cy optimization. the controller ties the upper and lower drive rails together. simply applying a voltage from 5v u p to 12v on pvcc s ets both gate drive rail voltages simultaneously. c boot_cap q gate ? v boot_cap -------------------------------------- ? q gate q g1 pvcc ? v gs1 ---------------------------------- n q1 ? = (eq. 13) 50nc 20nc figure 9. bootstrap capacitance vs boot ripple voltage ? v boot_cap (v) c boot_cap ( f) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0.3 0.0 0.1 0.2 0.4 0.5 0.6 0.9 0.7 0.8 1.0 q gate = 100nc
isl6322g fn6715 rev 0.00 page 22 of 39 may 22, 2008 initialization prior to initialization, proper c onditions must exist on the en , vcc, pvcc and the v id pins. when the conditions are met, the controller begins soft-sta rt. once the output voltage is within the proper window of operation, the controller asserts pgood. enable and disable while in shutdown mode, the pwm outputs are held in a high-impedance state to assure the drivers remain off. the following input conditions must be met, for both intel and amd modes of operation, bef ore the isl6322g is released from shutdown mode to begin the soft-start startup sequence: 1. the bias voltage applied at vcc must reach the internal power-on reset (por) risi ng threshold. once this threshold is reached, proper operation of all aspects of the isl6322g is guaranteed. hysteresis between the rising and falling thresholds a ssure that once enabled, the isl6322g will not inadverte ntly turn off unless the bias voltage drops substantially (see electrical specifications on page 6). 2. the voltage on en must be above 0.85v. the en input allows for power sequencing between the controller bias voltage and another voltage rail. the enable comparator holds the isl6322g i n shutdown until the voltage at en rises above 0.85v. the enable comparator has 110mv of hysteresis to prevent bounce. 3. the driver bias voltage appl ied at the pvcc pin must reach the internal power-on reset (por) rising threshold. hysteresis between the ris ing and falling thresholds assure that once enabled , the isl6322g will not inadvertently turn off unless the pvcc bias voltage drops substantially (see electrica l specifications on page 6). for intel vr10, vr11 and amd 6-bit modes of operation these are the only condition s that must be met for the controller to immediately begin the soft-start sequence. if running in amd 5-bit mode of operation there is one more condition that must be met: 4. the vid code must not be 11111 in amd 5-bit mode. this code signals the controller t hat no load is present. the controller will not allow soft-start to begin if this vid code is present on the vid pins. once all of these conditions are m et the controller will begin the soft-start sequence and will ramp the output voltage up to the user designated level. intel soft-start the soft-start function allows the converter to bring up the output voltage in a controlled fashion, resulting in a linear ramp-up. the soft-start sequ ence for the intel modes of operation is slightly differ ent then the am d soft-start sequence. for the intel vr10 and vr1 1 modes of ope ration, the soft-start sequence is composed of four periods, as shown in figure 11. once the isl6322 g is released from shutdown and soft-start begins (as described in the enable and disable on page 22), the contr oller will have fixed delay period t d1 . after this delay perio d, the vr will begin first soft-start ramp until the out put voltage reaches 1.1v vboot voltage. then, the controller will regulate the vr voltage at 1.1v for another fixed period t d3 . at the end of t d3 period, isl6322g will read the vid signals. if the v id code is valid, isl6322g will initiate the seco nd soft-start ramp until the output voltage reaches the vid voltage plus/minus any offset voltage. the soft-start time is the sum of the four periods as shown in equation 14. figure 10. power sequencing using threshold- sensitive enable (en) function external circuit isl6322g internal circuit - + 0.85v en +12v por circuit 10.7k ? 1.40k ? enable comparator soft-start and fault logic vcc pvcc figure 11. intel soft-start waveforms vout, 500mv/div en_vtt 500s/div pgood t d1 t d2 t d3 t d4 t d5 t ss t d1 t d2 t d3 t d4 +++ = (eq. 14)
isl6322g fn6715 rev 0.00 page 23 of 39 may 22, 2008 td1 is a fixed delay with the typical value as 1.40ms. td3 is determined by the fixed 85s plus the time to obtain valid vid voltage. if the vid is valid before the output reaches the 1.1v, the minimum time to valid ate the vid input is 500ns. therefore the minimu m td3 is about 86s. during t d2 and t d4 , isl6322g digitally controls the dac voltage change at 6.25mv per step. the time for each step is determined by the frequency of the soft-start oscillator which is defined by the resistor r ss from ss pin to gnd. the second soft-start ramp time t d2 and t d4 can be calculated based on equations 15 and 16: for example, when vid is set to 1.5v and the r ss is set at 100k ? , the first soft-start ramp time t d2 will be 704s and the second soft-start ramp time t d4 will be 256s. note: if the ss pin is grounded , the soft-start ramp in t d2 and t d4 will be defaulted to a 6.25mv step frequency of 330khz. after the dac voltage reaches the final vid setting, pgood will be set to high with the fixed delay t d5 . the typical value for t d5 is 440s. amd soft-start for the amd 5-bit and 6-bi t modes of operation, the soft-start sequence is composed of three periods, as shown in figure 12. at the beginning of soft-start, the vid code is immediately obtained from the vid pins, followed by a fixed delay period t da . after this delay per iod the isl6322g will begin ramping the output voltage to the desired dac level at a fixed rate of 6.25mv per step, with a stepping frequency of 330khz. the amount of time r equired to ramp the output voltage to the final dac voltage is referred to as tdb, and can be calculated as shown in equation 17. after the dac voltage reaches t he final vid s etting, pgood will be set to high wit h the fixed delay t dc . the typical value for t dc can range between 1.5ms and 3.0ms. pre-biased soft-start the isl6322g also has the a bility to start up into a pre-charged output, without causing any unnecessary disturbance. the fb pin is mon itored during soft-start, and should it be higher than the equivalent internal ramping reference voltage, the output drives hold both mosfets off. once the internal ramping re ference exceeds the fb pin potential, the output drives are enabled, allowing the output to ramp from the pre-charged le vel to the final level dictated by the dac setting. should the output be pre-charged to a level exceeding the dac sett ing, the output drives are enabled at the end of the soft -start period, leading to an abrupt correction in the output voltage down to the dac-set level. fault monitoring and protection the isl6322g actively monitors output voltage and current to detect fault condit ions. fault monitors trigger protective measures to prevent damage to a microprocessor load. one common power good indicator is provided for linking to external system monitors. the schematic in figure 14 outlines the interaction between the fault monitors and the power good signal. power good signal the power good pin (pgood) is an open-drain logic output that signals whether o r not the is l6322g is regulating the output voltage within the proper levels, and whether any fault t d2 1.1 r ? ss 6.25 25 ? ------------------------ ? s ?? = (eq. 15) t d4 2 ?? v vid 1.1 C ?? r ss ? 6.25 25 ? --------------------------------------------------- - ? s ?? = (eq. 16) figure 12. amd soft-start waveforms v out , 500mv/div en_vtt 500s/div t da t db t dc pgood (eq. 17) tdb 1 330 10 3 ? ------------------------- - v vid 0.00625 --------------------- ?? ?? ? = figure 13. soft-start waveforms for isl6322g-based multiphase converter en (5v/div) v out (0.5v/div) gnd> t1 gnd> t2 t3 output precharged below dac level output precharged above dac level
isl6322g fn6715 rev 0.00 page 24 of 39 may 22, 2008 conditions exist. this pin sho uld be tied to a +5v source through a resistor. during shutdown and soft-start pgood pulls low and releases high after a succe ssful soft-start and the output voltage is operating betw een the undervoltage and overvoltage limits. pgood transitions low when an undervoltage, overvoltage, o r overcurrent condition is detected or when the controller is disabled by a reset from en, por, or one of the no-cpu vid codes . in the event of an overvoltage or overcurrent condition, the controller latches off and pgood will no t return high u ntil after a successful soft-start. in the ca se of an undervoltage event, pgood will return high when t he output voltage returns to within the undervoltage. undervoltage detection the undervoltage threshold is set at 60% of the vid code. when the output voltage ( vsen - rgnd) is below the undervoltage threshold, pgood gets pulled low. no other action is taken by the controlle r. pgood will return high if the output voltage rises above 70% of the vid code. overvoltage protection the isl6322g constantly monitors the sensed output voltage on the vdiff pin to detect if a n overvoltage event occurs. when the output voltage rises above the ovp trip level actions are taken by the isl6322g to protect the microprocessor load. the overvo ltage protection trip level changes depending on what mode of operation the controller is in and what state the i 2 c registers and the vrsel pin are in. tables 6 and 7 list what the ovp trip levels are under all conditions (refer beginning on page 24 for details of controlling ovp thresholds with i 2 c). at the inception o f an overvoltage ev ent lgate1 and lgate2 are commanded high and the pgoo d signal is driven low. this turns on the a ll of the lower mosfets and pulls the output voltage belo w a level that might cause damage to the load. the lgate outputs remain high and until vdiff falls 100mv below the ovp threshold that tripped the overvoltage protect ion circuitry. the isl6322g will continue to protect the load in this fashion as long as th e overvoltage condition recurs. once an overvoltage conditi on ends, the isl6322g latches off and must be reset by t oggling en, or through por, before a soft-start can be re-initiated. one exception that overrides the overvoltage protection circuitry is a dynamic vid tr ansition in amd modes of operation. if a new vid co de is detected during normal operation, the ovp protection circuitry is disabled from the beginning of the dynamic vid tr ansition, until 50s after the internal dac reaches the final vid setting. this is the only time during operation of the isl6322g that the ovp circuitry is not active. pre-por overvoltage protection prior to pvcc and vcc exc eeding their por levels, the isl6322g is designed to protect the load from any overvoltage events that may o ccur. this is accomplished by means of an internal 10k ? resistor tied from phase to lgate, which turns on the lo wer mosfet to control the output voltage until the overvo ltage event ceases or the input power supply cuts off. for compl ete protection, the low side figure 14. power good and protection circuitry - + vdac vsen - + 0.60 x dac ov uv pgood soft-start, fault and control logic v ovp isl6322g internal circuitry - + rgnd x1 +175mv, +250mv, +350mv 120a or i sen1 +i sen2 vrsel vdiff i 2 c ovp register 240a - + v ocp ocp - + ocl i sen1 repeat for each channel 170a iout - + ocp table 6. intel vr10 an d vr11 ovp thresholds mode of operation default alternate soft-start (t d1 and t d2 ) 1.280v and vdac + 250mv (higher of the two) 1.280v and vdac + 175mv (higher of the two) soft-start (t d3 and t d4 ) vdac + 250mv vdac + 175mv normal operation vdac + 250mv vdac + 175mv table 7. amd ovp thresholds mode of operation default alternate soft-start 2.200v and vdac + 250mv (higher of the two) 2.200v and vdac + 175mv (higher of the two) normal operation vdac + 250mv vdac + 175mv
isl6322g fn6715 rev 0.00 page 25 of 39 may 22, 2008 mosfet should have a gate th reshold well below the maximum voltage rating of the load/microprocessor. in the event that during normal operat ion the pvcc or vcc voltage falls back below the por threshold, the pre-por overvoltage protection circuitr y reactivates to protect from any more pre-por ov ervoltage events. open sense line prevention in the case that either of the remote sense lines, vsen or gnd, become open, the isl 6322g is designed to prevent the controller from regulati ng. this is accomplished by means of a small 5a pull-up current on vsen, and a pull- down current on rgnd. if the sense lines are opened at any time, the voltage differenc e between vsen and rgnd will increase until an overvoltage ev ent occurs, at which point overvoltage protection activa tes and the controller stops regulating. the isl6322g will b e latched off and cannot be restarted until the controller is reset. overcurrent protection the isl6322g takes advant age of the proportionality between the load current and the total channel sense current, i sen1 +i sen2 , to detect an overcurrent condition. two different methods of detecting overcurrent events are available on the isl6322g. the first method continually compares the average sense current with an ocp reference current as shown in figur e 14. the value of the ocp reference current is dependant upon the number of channels operating. if the controller is operating in 2-phase mode the ocp reference current is 240a. if the controller is operating in single phase mode the ocp reference current is 120a. this ensures that the ocp trip current sca les properly with the number of channels firing. o nce the total sense current exceeds the ocp reference cu rrent, a comparator triggers the converter to begin overcu rrent protection procedures. this first metho d for detecting overcurrent events limits the minimum overcurrent trip threshold because of the fact the isl6322g uses s et internal r isen current sense resistors. for this first method the mini mum overcurrent trip threshold is dictated by the dcr of the inductors and the number of active channels. to calculate t he minimum overcurrent trip level, i ocp,min , use equation 18, where n is the number of active channels, dcr is the i ndividual inductors dcr, and r isen is the 300 ? internal current sense resistor. if the desired overcurrent t rip level is greater than the minimum overcurrent trip level, i ocp,min , then the resistor divider r-c circuit around the inductor shown in figure 15 should be used to set the desired trip level. if an overcurrent tr ip level lower then i ocp,min is desired, then a second method for se tting the ocp trip level is available. the second method for detecting overcurrent events continuously compares the vo ltage on the iout pin, v iout , to the overcurrent p rotection voltage, v ocp , as shown in figure 14. the total channel s ense current flows out the iout pin and through r iout , creating the iout pin voltage which is proportional to the o utput current. when the iout pin voltage exceeds the v ocp voltage of 2.0v, the overcurrent protection circuitry activates. since the iout pin voltage is proportional to the ou tput current, the overcurrent trip level, i ocp , can be set by selecting the proper value for r iout , as shown in equation 20. once the output current exce eds the overcurrent trip level, v iout will exceed v ocp and a comparator will trigger the converter to begin overcurr ent protection procedures. at the beginning of overcurrent shutdown, the controller sets all of the ugate and lgate signals low and forces pgood low. this turns off all of the upper and lower mosfets. the system remains in this state for a fixed period of 12ms. if the controller is still enabled at the end of this wait period, it will attempt a soft-start . if the fault remains, the trip-retry cycl es will continue indefinitely until either the controller is disab led or the fault is cleared. note that the energy delivered during trip-retry cycling is much less than during full-load operation , so there is no thermal hazard. individual channel overcurrent limiting the isl6322g has the ability to limit the current in each individual channel without shutting down the entire regulator. i ocp min ? 120 10 6 C r isen n ?? ? dcr ---------------------------------------------------------- = (eq. 18) (eq. 19) i ocp i ocp min ? ? i ocp 120 10 6 C r isen n ?? ? dcr ---------------------------------------------------------- ?? ?? ?? r 1 r 2 + r 2 -------------------- - ?? ?? ?? ? = i ocp v ocp r isen ? dcr r iout ? -------------------------------------- = (eq. 20) i ocp i ocp min ? ? 0a 0v 3ms/div output current, 50a/div figure 15. overcurrent behavior in hiccup mode output voltage, 500mv/div
isl6322g fn6715 rev 0.00 page 26 of 39 may 22, 2008 this is accomplished by conti nuously comparing the sensed currents of each channel with a constant 170a ocl reference current as shown in figure 14. if a channels individual sensed current exceeds this ocl limit , the ugate signal of that channel is immediately forced l ow, and the lgate signal is forced high. this turns off t he upper mosfet(s), turns on the lower mosfet(s), a nd stops the rise of current in that channel, forcing the current in the channel to decrease. that channels ugate signal will not be able to return high until th e sensed channel-current falls ba ck below the 170a reference. i 2 c bus interface the isl6322g includes an i 2 c bus interface which allows for user programmability of five o f the controllers operating parameters. the oper ating parameters that can be adjusted through the i 2 c are: 1. number of phases firing: selects whether the controller should run in single phase or 2-phase mode. the en_ph2 pin must be tied low for the number of phases firing to be controlled by the i 2 c bus interface. 2. voltage margining offset : the output voltage can be positively offset up to +78 7.5mv in 12.5mv increments. 3. adaptive deadtime control : selects between lgate detect and phase de tect deadtime co ntrol schemes as described in the user sele ctable adaptive deadtime control techniques on page 21. 4. overvoltage trip level : selects the overvoltage protection trip threshold as described in the overvoltage protection on page 24. 5. switching frequency: the switching frequency can be increased by a fixed +15% or +30%, or can be decreased by -15% or -30%. to adjust these five parameters, data transmission from the mai n microprocessor to the isl6322g and vice versa must take place through the two wire i 2 c bus interface. the two wires of the i 2 c bus consist of the sda line, over which all data is sent, and t he scl line, which is a clock signal use d to synchronize sending/receiving of the data. both sda and scl are bidirectional lines, externally connected to a positive supply voltage via a p ull-up resistor. pull-up resis tor values should be chosen to lim it the input current to less then 3ma ?? when the bus is free, both lines are high. the output stages of isl6322g have an open dr ain/open collector in order t o perform the wired-and f unction. data on the i 2 c bus can be transferred up to 100kbps in the standard-mode or up to 400kbps in the fast-mode. the level of l ogic 0 and logic 1 is depen dent on associated value of v dd as per the electric al specifications table on page 6. one clock pulse is generated for each data bit transferred. the isl63 22g is a slave only device, so the scl line must always be controlled by an external master. it is important to note that the i 2 c interface of the isl6322g only works once the voltage on the vcc pin has risen above the por rising t hreshold. the i 2 c will continue to remain active until the volt age on the vcc pin fa lls back below the falling por threshold level. data validity the data on the sda line must be stable during the high period of the scl, unless generating a start or stop condition. the high or low sta te of the data line can only change when the clock signal on the scl line is low. refer to figure 16. start and stop conditions as shown in figure 17, a start (s) condition is a high to low transition of the sda line while scl is high. the stop (p) condition is a low to high transition on the sda line while scl is high. a s top condition must be sent before each start condition. byte format every byte put on the sda line must be eight b its long. the number of bytes that can be transmitt ed per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferr ed with the most signi ficant bit first (m sb) and the least significant bit last (lsb). acknowledge each address and data transmissi on uses 9-clock pulses. the ninth pulse is the acknowledge bit (a). after the start conditi on, the master sends 7-slave address bits and a r/w bit during the next 8-clock pulses. during the ninth clock pulse, the device that recognizes its own addre ss holds the data line low to acknowledge. the acknowledge bi t is also used by both the master and the slave to acknow ledge receipt of register addresses and data as described as follows. sda scl data line stable data valid change of data allowed figure 16. data validity sda scl start condition figure 17. start and stop waveforms stop condition sp
isl6322g fn6715 rev 0.00 page 27 of 39 may 22, 2008 . isl6322g i 2 c slave address all devices on the i 2 c bus must have a 7-bit i 2 c address in order to be recognized. the isl6322g has two user selectable addresses to ensure it does not i nterfere with other devices on the bus. the address is programmed via the r ss resistor on the ss/rst/a0 pin. placing the r ss resistor from the ss/rst/a0 pin to ground sets the i 2 c address to be 1000_110. if the r ss resistor is placed from the ss/rst/a0 pin to vcc the address is 1000_111. please note that the i 2 c address of t he isl6322g is programmed from the ss/rst/a 0 pin as soon as vcc rises above the por threshold. the isl6322gs i 2 c address stays the same and can not be repr ogrammed until vcc falls back below the por falling threshold. communicating over the i 2 c bus two transactions are supported on the i 2 c interface: 1. write register, 2. read register from current address. all transactions start with a control byte sent from the i 2 c master device. the control byte begins with a start condition, followe d by 7-bits of slave address. the las t bit sent by the master is the r/w bit and is 0 for a write or 1 for a read. if any slaves on the i 2 c bus recognize their address, they will acknowledge by pulling the serial data line low for the last clock cycl e in the control by te. if no slaves exist at that address or a re not ready to communicate, t he data line will be 1, indicating a not acknowledge condition. once the control byte is sent, and the isl6322g acknowledges it, the 2nd byte s ent by the master must be a register address byte. this regi ster address byte tells the isl6322g which one of the two i nternal registers it wants to write to or read fro m. the address of the first internal regist er, rgs1, is 0000_0000. this register sets the voltage margining offset. the address of the second internal register, rgs2, is 0000_0001. this register sets th e adaptive deadtime control, overvoltage protection, and s witching frequency parameters. once the isl6322g receives a correct register address byte, it responds with an acknowledge. writing to the in ternal registers in order to change any of the four operating parameters via the i 2 c bus, the internal registers must be writt en to. the two registers inside the isl6322g c an be written indi vidually with two separate write transactions or sequentiall y with one write transaction by sending two dat a bytes as described below. to write to a single register in the isl6322g, the master sends a control byte with the r/w bit set to 0, indicating a write. i f it receives an acknowledge from the isl6322g, it sends a register address byte representing the internal register it wan ts to write to (0000_0000 for rgs1 or 0000_0001 for rgs2). the isl6322g will respond with an acknowledge. the master then sends a byte representing the data byte to be written into the desired register. the is l6322g will re spond with an acknowledge. the master then issues a stop condition, indicating to the isl6322g t hat the current transaction is complete. once this transaction completes, the isl6322g will immediately update and change the operating parameters on- the-fly. it is also possible to write to both registers sequentially. to do this the master must write to register rgs1 first. this transaction begins with the mast er sending a control byte with the r/w bit set to 0. if it rec eives an acknowledge from the isl6322g, it sends the regist er address byte 0000_0000, representing the internal regi ster rgs1. the isl6322g will respond with an acknow ledge. after sending the data byte to rgs1 and receiving an acknow ledge from the isl6322g, instead of sending a stop condition, the master sends the data byte to be stored in register rgs 2. the isl6322g will respond with an acknowledge. the ma ster then issues a stop condition, indicating to the isl6322g that the current transaction is complete. once t his transaction completes the isl6322g will immediately update and change the operating parameters on-the-fly. sda scl figure 18. acknowledge on the i 2 c bus 1 2 8 9 acknowledge from slave msb start
isl6322g fn6715 rev 0.00 page 28 of 39 may 22, 2008 i 2 c read and write protocol reading from the internal registers the isl6322g has the ability to read from both registers separately or read f rom them consecutive ly. prior to reading from an internal register, the master must first select the desired register by writing to i t and sending th e registers address byte. this process begi ns by the master sending a control byte with the r/w bit set to 0, indicating a write. onc e it receives an acknowledge from the isl6322g, it sends a register address byte representing the internal register it wan ts to read from (0000_0000 for rg s1 or 0000_0001 for rgs2). the isl6322g will respond with a n acknowledge. the master must then respond with a stop c ondition. after the stop condition, the master follows with a new start condition, and then sends a new control byte with the r/w bit set to 1, indicating a read. the isl6322g will then respon d by sending the master an acknowledge, fol lowed by the data byte stored in that register. the master must then send a not acknowledge followed by a stop command, which will complete the read transaction. it is also possible for both registers to be read consecutively . to do this the master must read from register rgs1 first. this transaction begins wit h the master sending a control byte with the r/w bit set to 0. if it rece ives an acknowledge from the isl6322g, it sends the regist er address byte 0000_0000, representing the internal regi ster rgs1. the isl6322g will respond with an acknowledge. the master mus t then respond with a stop condition. after t he stop condition the master follows with a new start cond ition, and then sends a new control byte with the r/w bit set to 1, indicating a read. the isl6322g will then respond by sending the master an acknowledge, followed by the data byte stored in register rgs. the master must then sen d an acknowledge, and after doing so, the isl6322g will resp ond by sending the data byte stored in register rgs2. the master must then send a not acknowledge followed by a stop command, which will complete the read transaction. resetting the internal registers the isl6322gs two internal i 2 c registers always initialize to 0000_0000 when the controller f irst receives power. once the voltage on the vcc pin rises above the por rising threshold level, these registers can be c hanged at any t ime via the i 2 c interface. if the voltage on the vcc pin falls below the por falling threshold, the internal r egisters are automatically res et to 0000_0000. it is possible to reset the inte rnal registers without powering down the controller and without r equiring the controller to sto p regulating and soft-start again. this can be done by one of two methods. the first m ethod is to simply w rite to the internal registers over the i 2 c interface to be 0000_0000. the other method is pull the voltage on the ss/rst/ a0 pin down below 0.4v. this will immediately rese t the internal registers to 0000_0000 and will not stop the c ontroller from regulating the output voltage or cause soft-start to recycle. s slave_addr + w a reg_addr a reg_data a p s slave_addr + w a a a s a n write to a single register write to both registers read from a single register driven by master driven by isl6322 0000_0000 reg_rgs1_data reg_rgs2_data a p reg_addr a p s slave_addr + w slave_addr + r a reg_data p s a read from both registers 0000_0000 a p s slave_addr + w slave_addr + r a reg_rgs1_data a reg_rgs2_data n p s = start condition a = acknowledge p = stop condition n = no acknowledge table 8. register rgs1 (voltage margining offset) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 v offset (mv) x x vo5 vo4 vo3 vo2 vo1 vo0 xx 0 0 0 0 0 00.0 xx 0 0 0 0 0 1 12.5 xx 0 0 0 0 1 0 25.0 xx 0 0 0 0 1 1 37.5 xx 0 0 0 1 0 0 50.00 xx 0 0 0 1 0 1 62.5 xx 0 0 0 1 1 0 75.0 xx 0 0 0 1 1 1 87.5 xx 0 0 1 0 0 0 100.0 xx 0 0 1 0 0 1 112.5
isl6322g fn6715 rev 0.00 page 29 of 39 may 22, 2008 xx 0 0 1 0 1 0 125.0 xx 0 0 1 0 1 1 137.5 xx 0 0 1 1 0 0 150.0 xx 0 0 1 1 0 1 162.5 xx 0 0 1 1 1 0 175.0 xx 0 0 1 1 1 1 187.5 xx 0 1 0 0 0 0 200.00 xx 0 1 0 0 0 1 212.5 xx 0 1 0 0 1 0 225.0 xx 0 1 0 0 1 1 237.5 xx 0 1 0 1 0 0 250.0 xx 0 1 0 1 0 1 262.5 xx 0 1 0 1 1 0 275.0 xx 0 1 0 1 1 1 287.5 xx 0 1 1 0 0 0 300.0 xx 0 1 1 0 0 1 312.5 xx 0 1 1 0 1 0 325.0 xx 0 1 1 0 1 1 337.5 xx 0 1 1 1 0 0 350.0 xx 0 1 1 1 0 1 362.5 xx 0 1 1 1 1 0 375.0 xx 0 1 1 1 1 1 387.5 xx 1 0 0 0 0 0 400.0 xx 1 0 0 0 0 1 412.5 xx 1 0 0 0 1 0 425.0 xx 1 0 0 0 1 1 437.5 xx 1 0 0 1 0 0 450.0 xx 1 0 0 1 0 1 462.5 xx 1 0 0 1 1 0 475.0 xx 1 0 0 1 1 1 487.5 xx 1 0 1 0 0 0 500.0 xx 1 0 1 0 0 1 512.5 xx 1 0 1 0 1 0 525.0 xx 1 0 1 0 1 1 537.5 xx 1 0 1 1 0 0 550.0 xx 1 0 1 1 0 1 562.5 xx 1 0 1 1 1 0 575.0 xx 1 0 1 1 1 1 587.5 table 8. register rgs1 (voltage margining offset) (continued) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 v offset (mv) x x vo5 vo4 vo3 vo2 vo1 vo0 xx 1 1 0 0 0 0 600.0 xx 1 1 0 0 0 1 612.5 xx 1 1 0 0 1 0 625.0 xx 1 1 0 0 1 1 637.5 xx 1 1 0 1 0 0 650.0 xx 1 1 0 1 0 1 662.5 xx 1 1 0 1 1 0 675.0 xx 1 1 0 1 1 1 687.5 xx 1 1 1 0 0 0 700.0 xx 1 1 1 0 0 1 712.5 xx 1 1 1 0 1 0 725.0 xx 1 1 1 0 1 1 737.5 xx 1 1 1 1 0 0 750.0 xx 1 1 1 1 0 1 762.5 xx 1 1 1 1 1 0 775.0 xx 1 1 1 1 1 1 787.5 table 8. register rgs1 (voltage margining offset) (continued) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 v offset (mv) x x vo5 vo4 vo3 vo2 vo1 vo0
isl6322g fn6715 rev 0.00 page 30 of 39 may 22, 2008 table 9. register rgs2 (# of phases/adaptive deadtime control/ov ervoltage protection/switching frequency) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 number of channels adaptive deadtime control overvoltage protection level switching frequency x ch0 dt1 dt0 ovp fs2 fs1 fs0 x 0 0 0 0 0 0 0 2-phase phase detect default nominal x 0 0 0 0 0 0 1 2-phase phase detect default -15% x 0 0 0 0 0 1 0 2-phase phase detect default -30% x 0 0 0 0 0 1 1 2-phase phase detect default +15% x 0 0 0 0 1 0 0 2-phase phase detect default +30% x 0 0 0 1 0 0 0 2-phase phase detect alternate nominal x 0 0 0 1 0 0 1 2-phase phase detect alternate -15% x 0 0 0 1 0 1 0 2-phase phase detect alternate -30% x 0 0 0 1 0 1 1 2-phase phase detect alternate +15% x 0 0 0 1 1 0 0 2-phase phase detect alternate +30% x 0 0 1 0 0 0 0 2-phase lgate detect default nominal x 0 0 1 0 0 0 1 2-phase lgate detect default -15% x 0 0 1 0 0 1 0 2-phase lgate detect default -30% x 0 0 1 0 0 1 1 2-phase lgate detect default +15% x 0 0 1 0 1 0 0 2-phase lgate detect default +30% x 0 0 1 1 0 0 0 2-phase lgate detect alternate nominal x 0 0 1 1 0 0 1 2-phase lgate detect alternate -15% x 0 0 1 1 0 1 0 2-phase lgate detect alternate -30% x 0 0 1 1 0 1 1 2-phase lgate detect alternate +15% x 0 0 1 1 1 0 0 2-phase lgate detect alternate +30% x 1 0 0 0 0 0 0 1-phase phase detect default nominal x 1 0 0 0 0 0 1 1-phase phase detect default -15% x 1 0 0 0 0 1 0 1-phase phase detect default -30% x 1 0 0 0 0 1 1 1-phase phase detect default +15% x 1 0 0 0 1 0 0 1-phase phase detect default +30% x 1 0 0 1 0 0 0 1-phase phase detect alternate nominal x 1 0 0 1 0 0 1 1-phase phase detect alternate -15% x 1 0 0 1 0 1 0 1-phase phase detect alternate -30% x 1 0 0 1 0 1 1 1-phase phase detect alternate +15% x 1 0 0 1 1 0 0 1-phase phase detect alternate +30% x 1 0 1 0 0 0 0 1-phase lgate detect default nominal x 1 0 1 0 0 0 1 1-phase lgate detect default -15% x 1 0 1 0 0 1 0 1-phase lgate detect default -30% x 1 0 1 0 0 1 1 1-phase lgate detect default +15% x 1 0 1 0 1 0 0 1-phase lgate detect default +30% x 1 0 1 1 0 0 0 1-phase lgate detect alternate nominal x 1 0 1 1 0 0 1 1-phase lgate detect alternate -15% x 1 0 1 1 0 1 0 1-phase lgate detect alternate -30%
isl6322g fn6715 rev 0.00 page 31 of 39 may 22, 2008 general design guide this section is intended to pro vide a high-level explanation of the steps necessary t o create a multiphase power converter. it is assumed that the reader is familia r with many of the basic skil ls and techniques referenced in the following. in add ition to this guide, intersil provides complet e reference designs that includ e schematics, bills of materials, a nd example board layouts for a ll common microprocessor applications. power stages the first step in designing a multiphase converter is to determine the number of phases . this determination depends heavily on the cost a nalysis, which in tu rn depends on system constraints that differ from one design to the next. principall y, the designer will be concerned with whet her components can be mounted on both si des of the circuit board, whether through-hole components are permitted, the total board space available for power-supply circu itry, and the maximum amount of load current. generally spe aking, the most economical solutions are those in which each phase handles between 25a and 30a. all surface-mount desi gns will tend toward the lower end of this current range. if through-hole mosfets and inductors can be used, higher per-phase currents are possible. in cases where board space is the limiting constraint, current can be pushed as high as 40a per phase, but these designs require heat sinks and forced air to cool the mosfets, inductors and heat-dissipating surfaces. mosfets the choice of mosfets depends on the current each mosfet will be required to conduct, the switching frequency, the capability of the mosfets to dissipate heat, and the availabili ty and nature of heat sinking and air flow. lower mosfet pow er calculation the calculation for power loss in the lower mosfet is simple, since virtually all of the loss in the lower mosfet is due to current conducted through the channel resistance (r ds(on) ). in equation 21, i m is the maximum conti nuous output current, i p- p is the peak-to-peak inductor current (see equation 1), and d is the duty cycle (v out /v in ). an additional term can be added to the lower-mosfet loss equation to account for additional loss accrued during the dead time when inductor current is flowing through the lower- mosfet body diode. this term is dependent on the diode forward voltage at i m , v d(on) , the switching frequency, f s , and the length of dead times, t d1 and t d2 , at the beginning and the end of the lower-mosfet conduct ion interval respectively. the total maximum power dissip ated in each lower mosfet is approximated by t he summation of p low,1 and p low,2 . upper mosfet power calculation in addition to r ds(on) losses, a large portion of the upper-mosfet losses are due to currents conducted across the input voltage (v in ) during switching. since a substantially higher portion of the upper-mosfet losses are dependent on switching frequency, the power c alculation is more complex. upper mosfet losses can be divided into separate components involving the upper-mosfet switching times, the lower-mosfet body-diode reverse-recovery charge, q rr , and the upper mosfet r ds(on) conduction loss. when the upper mosfet turns off, the lower mosfet does not conduct any portion of the i nductor current until the volta ge at the phase node falls below ground. once the lower mosfet begins conducting, the current in the upper mosfet falls to zero as the current in the lower mosfet ramps up to assume the full inductor current. in equation 23, the required time for this commutation is t 1 and the approximated associated power loss is p up,1 . at turn on, the upper mosfet begins to conduct and this transition occurs over a time t 2 . in equation 24, the approximate power loss is p up,2 . a third component invol ves the lower mosfet reverse-recovery charge, q rr . since the induct or current has fully commutated to the upper mosfet before the lower-mosfet body diode can recover all of q rr , it is x 1 0 1 1 0 1 1 1-phase lgate detect alternate +15% x 1 0 1 1 1 0 0 1-phase lgate detect alternate +30% note: it is recommended that frequenc y shifts occur in 15% incr ements only. table 9. register rgs2 (# of phases/adaptive deadtime control/ov ervoltage protection/switching frequency) (continued) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 number of channels adaptive deadtime control overvoltage protection level switching frequency x ch0 dt1 dt0 ovp fs2 fs1 fs0 (eq. 21) p low 1 ? r ds on ?? i m n ----- - ?? ?? ?? 2 1d C ?? ? i lp-p , 2 1d C ?? ? 12 ------------------------------------- - + ? = (eq. 22) p low 2 ? v don ?? f s i m n ------ i p-p 2 ----------- + ?? ?? ?? t d1 ? i m n ------ i p-p 2 ----------- C ?? ?? ?? ?? t d2 ? + ?? = (eq. 23) p up 1 , v in i m n ----- - i p-p 2 ---------- + ?? ?? t 1 2 ---- ?? ?? ?? f s ??? ? p up 2 , v in i m n ----- - i p-p 2 ---------- C ?? ?? ?? t 2 2 ---- ?? ?? ?? f s ??? ? (eq. 24)
isl6322g fn6715 rev 0.00 page 32 of 39 may 22, 2008 conducted through the upper mosfet across vin. the power dissipated as a result is p up,3 . finally, the resistive part of t he upper mosfet is given in equation 26 as p up,4 . the total power dissipated by t he upper mosfet at full load can now be approximated as the summation of the results from equations 23, 24, 25 and 26. since the po wer equations depend on mosfet parameters, choosi ng the correct mosfets can be an iterative process involving repetitive solutions to the loss equations for different mosfe ts and different switching frequencies. package power dissipation when choosing mosfets it is important to consider the amount of power being dissip ated in the integrated drivers located in the controller. since there are a to tal of three dri vers in the con troller package, the total power dissipate d by all three d rivers must b e less than the maximum allowable power dissipation for the qfn package. calculating the power dissipati on in the drivers for a desired application is critical to ensur e safe operation. exceeding the maximum allowable power dissipa tion level will push the ic beyond the maximum recomm ended operating junction temperature of +12 5c. the maximum allowable ic power dissipation for the 7x7 qfn pack age is approximately 3.5w at room temperature. see layout co nsiderations on page 36 for thermal transfer improvement suggestions. when designing the isl6322 g into an application, it is recommended that the following calculation is used to ensure sa fe operation at the desired frequen cy for the selected mosfets. the total gate drive power losses, p qg_tot , due to the gate charge of mosfets and the integrated drivers internal circuitr y and their corresponding average driver current can be estimated with equations 27 and 28, respectively. . in equations 27 and 28, p qg_q1 is the total upp er gate drive power loss and p qg_q2 is the total lower ga te drive power loss; the gate charge (q g1 and q g2 ) is defined at the particular gate to source drive voltage pvcc in t he corresponding mosfet data sheet; i q is the driver total quiescent current with no load at both drive outputs; n q1 and n q2 are the number of upper and lower mosfets per phase, respectively; n phase is the number of active phases. the i q* vcc product is the qui escent power of the controller without ca pacitive load and is t ypically 75mw at 300khz. the total gate drive power l osses are dissipated among the resistive components along th e transition path and in the bootstrap diode. the portion of the total power dissipated in t he controller itself is the power d issipated in the upper drive pa th resistance, p dr_up , the lower drive path resistance, p dr_up , and in the boot strap diode, p boot . the rest of the power will be di ssipated by the external gate resistors (r g1 and r g2 ) and the internal gate resistors (r gi1 p up 3 , v in q rr f s ?? = (eq. 25) p up 4 , r ds on ?? d i m n ----- - ?? ?? ?? 2 i p-p 2 12 ---------- + ?? ? (eq. 26) p qg_tot p qg_q1 p qg_q2 i q vcc ? ++ = (eq. 27) p qg_q1 3 2 -- - q g1 pvcc f sw n q1 n phase ?? ??? = p qg_q2 q g2 pvcc f sw n q2 n phase ???? = -- - q g1 n ? q1 ? q g2 n q2 ? + ?? ?? n phase f sw i q + ?? = (eq. 28) figure 19. typical upper-gate drive turn-on path figure 20. typical lower-g ate drive turn-on path q1 d s g r gi1 r g1 boot r hi1 c ds c gs c gd r lo1 phase pvcc ugate pvcc q2 d s g r gi2 r g2 r hi2 c ds c gs c gd r lo2 lgate p dr p dr_up p dr_low p boot i q vcc ? ?? +++ = (eq. 29) p dr_up r hi1 r hi1 r ext1 + -------------------------------------- r lo1 r lo1 r ext1 + ---------------------------------------- + ?? ?? ?? p qg_q1 3 --------------------- ? = p dr_low r hi2 r hi2 r ext2 + -------------------------------------- r lo2 r lo2 r ext2 + ---------------------------------------- + ?? ?? ?? p qg_q2 2 --------------------- ? = r ext1 r g1 r gi1 n q1 ------------- + = r ext2 r g2 r gi2 n q2 ------------- + = p boot p qg_q1 3 --------------------- =
isl6322g fn6715 rev 0.00 page 33 of 39 may 22, 2008 and r gi2 ) of the mosfets. figu res 19 and 20 show the typical upper and lower gate drives turn-on transition path. th e total power dissipation in the controller itself, p dr , can be roughly estimated with equation 29. inductor dcr curren t sensing component selection the isl6322g senses each individual channels inductor current by detecting the voltage across the output inductor dcr of that channel ( as described in continuous current sampling on page 12). as figur e 21 illustrates, an r-c network is required to accurat ely sense the inductor dcr voltage and convert this informat ion into a current, which is proportional to the total output c urrent. the time constant of this r-c network must match the time constant of the inductor l/dcr. the r-c network across the indu ctor also sets the overcurrent trip threshold for the regulator. before the r-c components can be selected, the desired overcurr ent protection level should be chosen. the minimum overcurrent trip threshold the controller can support is dictated by t he dcr of the induc tors and the number of active channels. t o calculate the minimum overcurrent trip level, i ocp,min , use equation 30, where n is the number of active channel s, and dcr is the individual inductors dcr. if the desired overcurrent trip level is equal to or less than the minimum overcurrent trip level, follow the steps below to choose the component va lues for the r-c current sensing network: 1. choose an arbitrary value for c 1 . the recommended value is 0.1f. 2. plug the inductor l and dcr component values, and the value for c 1 chosen in step 1, into equation 31 to calculate the value for r 1 . 3. resistor r 2 should be left unpopulated. if the desired overcu rrent trip level, i ocp , is greater than the minimum overcurrent trip level, i ocp,min , then a resistor divider r-c circuit should be used to s et the desired trip level. take the following steps to c hoose the component values for the resistor divider r-c current sensing network: 1. choose an arbitrary value for c 1 . the recommended value is 0.1f. 2. plug the inductor l and dcr component values, the value for c 1 chosen in step 1, the number of active channels n, and the desired overcurrent protection level i ocp into equations 32 and 33 to calculate the values for r 1 and r 2 . . iout pin resistor a copy of the total channel sense current, i sen1 +i sen2 , flows out of the iout pin, and a resistor, r iout , placed from this pin to ground can be used to set t he overcurrent protection trip level. based on the desired overcurrent trip threshold, i ocp , the iout pin resistor, r iout , can be calculated from equation 34 or equation 35, depending on the r-c current sense circuitry being employed. if a basic r-c sense circuit consisti ng of c 1 and r 1 is being used, use equation 36. if a resistor divider r-c sense circuit consisting of r 1 , r 2 , and c 1 is being used, use equation 36. compensation the two opposing goals of compensating the voltage regulator are stability and speed. the re gulated converter is accurately modeled as a voltage-mode regulator with two poles at the l-c resonant frequency and a zero at the esr frequency. a type iii controller, as shown in figure 23, provides the necessary compensation. i ocp min ? 0.036 n ? dcr ----------------------- = (eq. 30) figure 21. dcr sensing configuration i n - + isen-(n) sample isl6322g internal circuit v in ugate(n) r isen dcr l inductor r 1 v out c out - + v c (s) c 1 i l - + v l (s) i sen r 2* v c (s) + - *r 2 is optional isen+(n) lgate(n) mosfet driver r 1 l dcr c 1 ? ------------------------- = (eq. 31) i ocp i ocp min ? = ? c 1 0.036 n ?? ----------------------------------- = (eq. 32) i ocp i ocp min ? ? ???? ? c 1 i ocp dcr 0.036 n ? C ? ?? ? --------------------------------------------------------------- --------------- - = (eq. 34) r iout 600 dcr i ocp ? -------------------------------- = i ocp i ocp min ? ? ???? ? ? -------------------------------- r 1 r 2 + r 2 -------------------- - ?? ?? ?? ? = i ocp i ocp min ? ?
isl6322g fn6715 rev 0.00 page 34 of 39 may 22, 2008 the first step is to choose the desired bandwidth, f 0 , of the compensated system. choose a frequency high enough to assure adequate transient performance but not higher than 1/3 of the switching frequency. the type-iii compensator has an extra high-frequency pole, f hf . this pole can be used for added noise rejection or to assure adequate attenuation at the error-amplifier high-order pole and zero frequencies. a good general rule is to choose f hf =10f 0 , but it can be higher if desired. choosing f hf to be lower than 10f 0 can cause problems with too much phase shift below the system bandwidth. in the solutions to the comp ensation equations, there is a single degree of fr eedom. for the solutions presented in equation 36, r fb is selected arbitra rily. the remaining compensation components are then selected according to equation 36. in equation 36, l is the per-channel filter inductance divided by the number of active channels; c is the su m total of all output capacitors; esr is the equivalent- series resistanc e of the bulk output-filter cap acitance; and v p-p is the peak-to-peak sawtooth signal amplitude as described in electrical specifications on page 6. output filter design the output inductors and the out put capacitor bank together to form a low-pass filter responsib le for smoothing the pulsating voltage at the phase nodes. the output filter also must provide the transient energy until the re gulator can respond. because i t has a low bandwidth compared to the switching frequency, the output filter limits the system t ransient respons e. the output capacitors must supply or sink load current while the current i n the output inductor s increases or decreases to meet the demand. in high-speed converters, the ou tput capacitor bank is usually the most costly (and often the largest) part of the circuit. ou tput filter design begins with mini mizing the cost o f this part of t he circuit. the critical load par ameters in choosing the output capacitors are the maximu m size of the load step, ? i, the load- current slew rate, di/dt, and the maximum allowable output- voltage deviation under transient loading, ? v max . capacitors are characterized according to their capacitance, esr, and esl (equivalent series inductance). at the beginning of the load tr ansient, the output capacitors supply all of the transient cur rent. the output voltage will initially deviate by an amount approximated by the voltage drop across the esl. as the load cu rrent increases, the voltage drop across the esr increases li nearly until the load current reaches its final value. the c apacitors selected must have sufficiently low esl and esr so that the total output-voltage deviation is less t han the allowable maxi mum. neglecting the contribution of induct or current and regul ator response, the output voltage initially devia tes by the amount specified in equation 37. the filter capacitor must have sufficiently low esl and esr so that ? v < ? v max . most capacitor solutions rely on a mixture of high-frequency capacitors with relati vely low capacitance in combination with bulk capacitors having high c apacitance but limited high- frequency performance. minimizing the esl of the high- frequency capacitors allows them to support the output voltage as the current increases. min imizing the esr of the bulk capacitors allows them to supp ly the increased current with less output voltage deviation. the esr of the bulk capacitors a lso creates the majority of the output-voltage ripple. as the bul k capacitors sin k and source the inductor ac ripple current (see interleaving on page 10 and equation 38), a voltage develops across the bulk capacitor esr equal to i c(p-p) (esr). thus, once the output capacitors are selected, the maximum allowable ripple voltage, v (p- p)(max) , determines the lower limit on the inductance. figure 22. compensation circuit isl6322g comp c c r c r fb fb vdiff c 2 c 1 r 1 c c v in 2 ? f hf lc ? 1 C ?? ? ?? ? 2 ? ? ?? 2 f 0 f hf lc ? ?? r fb v p-p ?? ? ? ? --------------------------------------------------------------- -------------------------------------- = r c v pp 2 ? ?? ?? ? 2 f 0 f hf lcr fb ?? ??? v in 2 ? f hf lc ? 1 C ?? ? ?? ? --------------------------------------------------------------- ------------------------- - = r 1 r fb cesr ? lc ? c esr ? C ------------------------------------------- - ? = c 1 lc ? c esr ? C r fb ------------------------------------------- - = c 2 v in 2 ? ? ?? 2 f 0 f hf lc ? ?? r fb v p-p ?? ? ? ? --------------------------------------------------------------- -------------------------------------- = (eq. 36) ? vesl di dt ---- - ? esr ? i ? + ? (eq. 37) l esr v in nv ? out C ?? ?? v out ? f s v in v p-p ?? max ?? ?? --------------------------------------------------------------- ---- - ? ? (eq. 38)
isl6322g fn6715 rev 0.00 page 35 of 39 may 22, 2008 since the capacitors are supplyi ng a decreasing portion of the load current while the regulator recovers from the transient, t he capacitor voltage becomes slig htly depleted. the output inductors must be capable of a ssuming the entir e load current before the output voltage decreases more than ? v max . this places an upper limit on inductance. equation 39 gives the upper limit on l for the cases when the trailing edge of the current transient causes a greater output- voltage deviation than the leading edge. equation 40 addresses the leading edge. normally, the trailing edge dictates the selection of l bec ause duty cycles are usually les s than 50%. nevertheless, both inequalities should be evaluated, and l should be selec ted based on the lower of the two results. in each equation: l is the per-channel inductance, c is the total outpu t capacitance, and n is the number of active channels. switching frequency there are a number of variabl es to consider when choosing the switching frequenc y, as there are considerable effects on the upper mosfet loss calculation. these effects are outlined in mosfets on page 31, and t hey establish the upper limit for the switching frequency. the l ower limit is established by the requirement for fast transie nt response and small output- voltage ripple as outlined in compensation on page 33. choose the lowest switching frequency that allows the regulator to meet the trans ient-response requirements. switching frequency is determi ned by the selection of the frequency-setting resistor, r t . figure 23 and equation 41 are provided to assist in select ing the correct value for r t . input capacitor selection the input capacitors are res ponsible for sourcing the ac component of the input curre nt flowing in to the upper mosfets. their rms current capacity must be sufficient to handle the ac component of the current drawn by the upper mosfets which is related to duty cycle and the number of active phases. for a two-phase design, use fig ure 24 to dete rmine the input- capacitor rms current require ment set by the duty cycle, maximum sustained output current (i o ), and the ratio of the peak-to-peak inductor current (i l,(p-p) ) to i o . select a bulk capacito r with a ripple current rating which will minimize the total number of i nput capacitor s required to support the rms current calcul ated. the voltage rating of the capacitors should also be at l east 1.25x greater than the maximum input voltage. figure 25 provides the same input rms current information for single-phase designs. use the same approach for selecting the bulk capacitor type and number. l 2ncv o ??? ? i ?? 2 --------------------------------- ? v max ? iesr ? ?? C ? ? (eq. 39) l 1.25 nc ?? ? i ?? 2 ---------------------------- - ? v max ? i esr ? ?? C v in v o C ?? ?? ?? ? (eq. 40) r t 10 10.61 1.035 f s ?? log ? ?? C ?? = (eq. 41) figure 23. r t vs switching frequency switching frequency (hz) r t (k ? ) 10 100 1000 10k 100k 1000k 10000k figure 24. normalized input-capacitor rms current for 2-phase converter 0.3 0.1 0 0.2 input-capacitor current (i rms/ i o ) 00.4 1.0 0.2 0.6 0.8 duty cycle (v in/ v o ) i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o
isl6322g fn6715 rev 0.00 page 36 of 39 may 22, 2008 low capacitance, high-frequency ceramic capacitors are needed in addition to the input bulk capacitors to suppress leading and falling edge voltage spikes. the spikes result from the high current slew rate prod uced by the upper mosfet turn on and off. select low esl ceramic capacitors and place one as close as possible to each upp er mosfet drain to minimize board parasitics and m aximize suppression. layout considerations mosfets switch very fast and efficiently. the speed with which the current transitions f rom one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit element s. these voltage spikes can degrade efficiency, radiate nois e into the circuit and lead to device overvoltage stress. careful component selection, layout, and placement minimizes these voltage spikes. consider, as an example, the t urnoff transition of the upper pwm mosfet. prior to turnoff, the upper mosfet was carrying channel-current. during the turnoff, current stops flowing in the upper mosfet a nd is picked up by the lower mosfet. any inductance in the switched current path generates a large voltage spike during the switching interval. careful component se lection, tight layout of the critical components, and short, wide ci rcuit traces minimize the magnitude of voltage spikes. there are two sets of critical components in a dc/dc converter using an isl6322g controller. the power components are the most critical because they swit ch large amounts of energy. next are small signal component s that connect to sensitive nodes or supply critical bypass ing current and signal coupling. the power components sh ould be placed first, which include the mosfets, input and output capacitors, and the inductors. it is important to have a symmetric al layout for each power train, preferably with the controller located equidistant from each. symmetrical layout allows heat to be dissipated equally across all power trains. equidistant placement of the controller to th e first three power trains it contro ls through the integrated dri vers helps keep the gate drive traces equally short, resulting in eq ual trace impedances and similar driv e capability of all sets of mosfets. when placing the mosfets, try to keep the source of the upper fets and the drain of the lower fets as close as thermally possible. input bulk capacitors should be placed close to the drain of the upper fets and the source of the lower fets. locat e the output inductor s and output capacitors between the mosfets and the load. the high -frequency input and output decoupling capacitors (ceramic) should be placed as close as practicable to the decoupling target, making use of the shortes t connection paths to any internal planes, such as vias to gnd ne xt or on the capacitor solder pad. the critical small components in clude the bypass capacitors for vcc and pvcc, and many of the components surrounding the controller inc luding the feedback network and current sense components. locate the vcc/pvcc bypass capacitors as close to the isl6322g as possible. it is especially importan t to locate the components asso ciated with the feedback circuit close to their respective controller pins, since they belong to a high-impedance circuit loop, sensitive to emi pick-up. a multi-layer printed circuit board is recomm ended. figure 27 shows the connections of the c ritical components for the converter. note that capacitors c xxin and c xxout could each represent numerous physical capacitors. dedicate one solid laye r, usually the one underneath the component side of the board, for a ground plane and make all critical component ground connections with vias to this layer. dedicat e another solid layer as a powe r plane and break this plane into smaller islands of common volta ge levels. keep the metal runs fr om the phase term inal to output inductors short. the power plane should support the input power and output power nodes. use copper filled polygons on the top and bottom circuit layers for th e phase nodes. use the remainin g printed circuit layers f or small signal wiring. routing ugate, lgate, and phase traces great attention should be paid to routing the ugate, lgate, and phase traces since they dri ve the power train mosfets using short, high current pulse s. it is important to size them as large and as short as possible to reduce their overall impedanc e and inductance. they should be sized to carry at least one ampere of current (0.02 to 0.05). going between layers with vias should also be avoided, b ut if so, use two vias for interconnection when possible. extra care should be given to the lgate traces in particular since keeping their impedance and inductance low helps to significantly reduce the possibility of shoot-through. it is al so important to route each channel s ugate and phase traces in as close proximity as possible to reduce their inductances. figure 25. normalized input-capacitor rms current for single-phase converter 00.4 1.0 0.2 0.6 0.8 duty cycle (v in /v o ) input-capacitor current (i rms /i o ) 0.6 0.2 0 0.4 i l(p-p) = 0 i l(p-p) = 0.5 i o i l(p-p) = 0.75 i o
fn6715 rev 0.00 page 37 of 39 may 22, 2008 isl6322g intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2008. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. current sense component placement and trace routing one of the most critical aspect s of the isl6322g regulator layout is the placement of the inductor dcr current sense components and traces. the r- c current sense components must be placed as cl ose to their respective isen+ and isen- pins on the isl6322g as possible. the sense traces that connect the r-c sense components to each side of the output induc tors should be routed on the bottom of the board, away f rom the noisy switching components located on the top of the board. these traces should be routed sid e by side, and they should be very thin traces. its important to route these traces as far away from a ny other noisy traces or planes as possible. these traces should pick up as little noise as possible. thermal management for maximum thermal performa nce in high current, high switching frequency applications , connecting the thermal gnd pad of the isl6322g to the ground plane with multiple vias is recommended. this heat spreading allows the part to achieve its full thermal potential. it is also recommended that the controller be placed in a direct path of airflow if possible to help thermally manage the part.
isl6322g fn6715 rev 0.00 page 38 of 39 may 22, 2008 via connection to ground plane island on power plane layer island on circuit plane layer key figure 26. printed circuit board power planes and islands heavy trace on circuit plane layer c boot1 r 1 c 1 c 3 r ofs r fb c bin1 (c hfout ) c bout (cf1) (cf2) r t c ref locate close to ic locate near load; (minimize connection locate near switching transistors; (minimize connection path) (minimize connection path) vid4 vid5 pgood vid3 vid2 vid1 vcc isl6322g vid0 fs ofs ref load vrsel en +12v gnd vid6 vid7 +5v isen2- isen2+ isen1- isen1+ fb comp vsen rgnd vdiff +12v phase1 ugate1 boot1 lgate1 +12v phase2 ugate2 boot2 lgate2 pvcc r ss c boot2 c bin2 c 1 r 1 c 1 r 1 path) r en1 r en2 ss / rst / a0 scl sda r iout en_ph2 iout r 2 c 2 nc
isl6322g fn6715 rev 0.00 page 39 of 39 may 22, 2008 package outline drawing l48.7x7 48 lead quad flat no-lead plastic package rev 4, 10/06 located within the zone indicate d. the pin #1 identifier may be unless otherwise specified, t olerance : decimal 0.05 tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing c onform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: 7.00 b a 7.00 (4x) 0.15 index area pin 1 top view pin #1 index area 44x 0.50 4x 5.5 48 37 4. 30 0 . 15 1 36 25 48x 0 . 40 0 . 1 4 m 0.10 c ab 13 24 bottom view 12 5 0 . 2 ref 0 . 00 min. 0 . 05 max. detail "x" c 0 . 90 0 . 1 base plane see detail "x" c c 0.08 seating plane c 0.10 side view typical recommended land pattern 6 6 ( 6 . 80 typ ) ( 4 . 30 ) ( 48x 0 . 60 ) ( 44x 0 . 5 ) ( 48x 0 . 23 ) 0.23 +0.07 / -0.05

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